| RTL to Transistor Level Power Modelling and Estimation Techniques for FPGA and ASIC: A Survey Y NASSER, J Lorandel, JC Prevotet, M Hélard IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 41 | 2021 |
| Dynamic power estimation based on switching activity propagation Y Nasser, JC Prévotet, J Lorandel, M Hélard 2017 27th International Conference on Field Programmable Logic and …, 2017 | 19 | 2017 |
| AES algorithm implementation for a simple low cost portable 8-bit microcontroller YA Nasser, MA Bazzoun, S Abdul-Nabi 2016 Sixth International Conference on Digital Information Processing and …, 2016 | 15 | 2016 |
| NeuPow: A CAD Methodology for High Level Power Estimation Based on Machine Learning Y NASSER, C Sau, JC Prévotet, T Fanni, F Palumbo, M Hélard, L Raffo ACM Transactions on Design Automation of Electronic Systems 25 (5), 29, 2020 | 8 | 2020 |
| Power Modeling on FPGA: A Neural Model for RT-Level Power Estimation Y Nasser, JC Prévotet, M Hélard ACM International Conference on Computing Frontiers, 2018, Ischia, Italy., 2018 | 8 | 2018 |
| NeuPow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology Y NASSER, C Sau, JC Prévotet, T Fanni, F Palumbo, M Hélard, L Raffo ACM International Conference on Computing Frontiers 2019, 2019 | 5 | 2019 |
| NFC/RFID benchmark design and verification strategy against EMVCo standard Y Nasser, M Bazzoun, H Hijazi, AC Al Ghouwayel, A Dhayni 2017 11th European Conference on Antennas and Propagation (EUCAP), 398-402, 2017 | 5 | 2017 |
| Modeling and design of NFC/RFID backbone using a Computer Aided Design tool YA Nasser, MA Bazzoun, H Hijazi, A Al Ghouwayel 2016 Sixth International Conference on Digital Information Processing and …, 2016 | 2 | 2016 |
| Toward Hardware-Assisted Malware Detection Utilizing Explainable Machine Learning: A Survey Y Nasser, M Nassar IEEE Access 11, 131273 - 131288, 2023 | 1 | 2023 |
| Power Modeling for Fast Power Estimation on FPGA Y Nasser, JC Prevotet, M Hélard | 1 | 2018 |
| Power Estimation on FPGAs Based on Signal Information Propagation Through Digital Operators Y Nasser, JC Prévotet, J Lorandel, M Hélard First International Conference on Sensors, Networks, Smart and Emerging …, 2017 | 1 | 2017 |
| Key Attack Strategies Against Black-Box DNNs Y Hmamouche, Y Nasser, A Baghdadi, MO Pahl GDR-SOC2, 2022 | | 2022 |
| An Efficient Computer-Aided Design Methodology for FPGA&ASIC High-Level Power Estimation Based on Machine Learning Y NASSER L’institut d’électronique et de télécommunications de Rennes, IETR, CNRS 6164, 2020 | | 2020 |
| A Neural Model for RT-Level Power Estimation on FPGAs Y Nasser, JC Prevotet, M Hélard 13ème Colloque du GDR SoC/SiP 2018, Jun 2018, Paris, France. ⟨hal-02021099⟩, 2018 | | 2018 |
| Power Aware Framework for Fast & Early Power Estimation on FPGA Y Nasser, JC Prévotet, M Hélard DATE 2018, PhD Forum, 2018 | | 2018 |
| Power Modeling for Fast Power Estimation on FPGA Y Nasser, JC Prévotet, M Hélard PhD Forum Day, DATE 2018, Dresden, Germany., 2018 | | 2018 |
| Statistical Information Propagation Across Operators for Dynamic Power Estimation on FPGAs Y Nasser, JC Prevotet, J Lorandel, M Helard 12ème Colloque du GDR SoC/SiP - Colloque 2017 à Bordeaux, France, 2017 | | 2017 |
| Power Modeling for Fast & Early Power Estimation of FPGA-based Communications Systems Y Nasser, JC Prévotet, M Hélard 12ème Colloque du GDR SoC/SiP, Bordeaux, France., 2017 | | 2017 |
Maryline HELARDprofesseur, ingénieurVerified email at insa-rennes.fr
