Razvan Nane
Razvan Nane
Cofounder, BDA, The Netherlands
Verified email at bigdataccelerate.com
Cited by
Cited by
A survey and evaluation of FPGA high-level synthesis tools
R Nane, VM Sima, C Pilato, J Choi, B Fort, A Canis, YT Chen, H Hsiao, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler
R Nane, VM Sima, B Olivier, R Meeuws, Y Yankova, K Bertels
22nd International Conference on Field Programmable Logic and Applications …, 2012
On the implementation of computation-in-memory parallel adder
HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017
Computation-in-memory based parallel adder
HA Du Nguyen, L Xie, M Taouil, R Nane, S Hamdioui, K Bertels
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
Parallel matrix multiplication on memristor-based computation-in-memory architecture
A Haron, J Yu, R Nane, M Taouil, S Hamdioui, K Bertels
2016 International Conference on High Performance Computing & Simulation …, 2016
REFLECT: Rendering FPGAs to multi-core embedded computing
JMP Cardoso, PC Diniz, Z Petrov, K Bertels, M Hübner, H van Someren, ...
Reconfigurable Computing, 261-289, 2011
OpenQL: A portable quantum programming framework for quantum accelerators
N Khammassi, I Ashraf, JV Someren, R Nane, AM Krol, MA Rol, L Lao, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-24, 2021
Controlling a complete hardware synthesis toolchain with LARA aspects
JMP Cardoso, T Carvalho, JGF Coutinho, R Nobre, R Nane, PC Diniz, ...
Microprocessors and Microsystems 37 (8), 1073-1089, 2013
High-level synthesis in the delft workbench hardware/software co-design tool-chain
R Nane, VM Sima, CP Quoc, F Goncalves, K Bertels
2014 12th IEEE International Conference on Embedded and Ubiquitous Computing …, 2014
A new approach to control and guide the mapping of computations to FPGAs
JMP Cardoso, R Nane, PC Diniz, Z Petrov, K Krátkı, K Bertels, M Hübner, ...
Proceedings of the International Conference on Engineering of Reconfigurable …, 2011
Skeleton-based design and simulation flow for computation-in-memory architectures
J Yu, R Nane, A Haron, S Hamdioui, H Corporaal, K Bertels
2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016
Quipu: A statistical model for predicting hardware resources
R Meeuws, SA Ostadzadeh, C Galuzzi, VM Sima, R Nane, K Bertels
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 6 (1), 1-25, 2013
Sparstition: a partitioning scheme for large-scale sparse matrix vector multiplication on FPGA
B Sigurbergsson, T Hogervorst, TD Qiu, R Nane
2019 IEEE 30th International Conference on Application-specific Systems …, 2019
An image processing vliw architecture for real-time depth detection
D Iorga, R Nane, Y Lu, E Van Dalen, K Bertels
2016 28th International Symposium on Computer Architecture and High …, 2016
The REFLECT Design-Flow
JMP Cardoso, JGF Coutinho, R Nane, VM Sima, B Olivier, T Carvalho, ...
Compilation and Synthesis for Embedded Reconfigurable Systems, 13-34, 2013
IP-XACT extensions for Reconfigurable Computing
R Nane, S van Haastregt, T Stefanov, B Kienhuis, VM Sima, K Bertels
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
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JM Cardoso, R Nane, PC Diniz, Z Petrov, K Krátky, K Bertels, M Hübner, ...
F. Coutinho, G. Constantinides et al.,“A New Approach to Control and Guide …, 2011
Low-cost software control-flow error recovery
G Nazarian, R Nane, GN Gaydadjiev
2015 Euromicro Conference on Digital System Design, 510-517, 2015
Deriving resource efficient designs using the REFLECT aspect-oriented approach
JGF Coutinho, JMP Cardoso, T Carvalho, R Nobre, S Bhattacharya, ...
International Symposium on Applied Reconfigurable Computing, 226-228, 2013
Hardware/Software Compilation
R Nobre, JMP Cardoso, B Olivier, R Nane, L Fitzpatrick, JGF Coutinho, ...
Compilation and Synthesis for Embedded Reconfigurable Systems, 105-134, 2013
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