Resistive bridge fault model evolution from conventional to ultra deep submicron I Polian, P Engelke, B Becker, S Kundu, JM Galliere, M Renovell 23rd IEEE VLSI Test Symposium (VTS'05), 343-348, 2005 | 58 | 2005 |
Delay testing of MOS transistor with gate oxide short Renovell, Galliere, Azais, Bertrand 2003 Test Symposium, 168-173, 2003 | 33 | 2003 |
Boolean and current detection of MOS transistor with gate oxide short M Renovell, JM Galliere, F Azaïs, Y Bertrand Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 1039-1048, 2001 | 33 | 2001 |
Modeling gate oxide short defects in CMOS minimum transistors M Renovell, JM Gallière, F Azaïs, Y Bertrand Proceedings The Seventh IEEE European Test Workshop, 15-20, 2002 | 32 | 2002 |
Neutron-induced multiple bit upsets on two commercial SRAMs under dynamic-stress P Rech, JM Galliere, P Girard, A Griffoni, J Boch, F Wrobel, F Saigné, ... IEEE Transactions on Nuclear Science 59 (4), 893-899, 2012 | 24 | 2012 |
Modeling the random parameters effects in a non-split model of gate oxide short M Renovell, JM Gallière, F Azaïs, Y Bertrand Journal of Electronic Testing 19 (4), 377-386, 2003 | 24 | 2003 |
Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI--LVT and RVT Configurations A Karel, M Comte, JM Galliere, F Azais, M Renovell 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 164-169, 2016 | 17 | 2016 |
Thermal scans for detecting hardware Trojans M Cozzi, JM Galliere, P Maurine Constructive Side-Channel Analysis and Secure Design: 9th International …, 2018 | 14 | 2018 |
Analysis of short defects in FinFET based logic cells F Forero, JM Galliere, M Renovell, V Champac 2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017 | 14 | 2017 |
Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect A Karel, M Comte, JM Galliere, F Azais, M Renovell 2016 17th Latin-American Test Symposium (LATS), 129-134, 2016 | 12 | 2016 |
Impact of resistive-open defects on SRAM error rate induced by alpha particles and neutrons P Rech, JM Galliere, P Girard, F Wrobel, F Saigne, L Dilillo IEEE Transactions on Nuclear Science 58 (3), 855-861, 2011 | 12 | 2011 |
Neutron detection through an SRAM-based test bench L Dilillo, F Wrobel, JM Galliere, F Saigné 2009 3rd International Workshop on Advances in sensors and Interfaces, 64-69, 2009 | 12 | 2009 |
Resistive bridging defect detection in bulk, fdsoi and finfet technologies A Karel, M Comte, JM Galliere, F Azais, M Renovell Journal of Electronic Testing 33, 515-527, 2017 | 10 | 2017 |
Analysing the characteristics of MOS transistors in the presence of gate oxide short M Renovell, JM Gallière, F Azaïs, Y Bertrand Design & Diag. of Electr. Circuits and Syst, 155-161, 2001 | 10 | 2001 |
A 2-D KLM model for disk-shape piezoelectric transducers JM Galliere, L Latorre, P Papet 2009 Second International Conference on Advances in Circuits, Electronics …, 2009 | 9 | 2009 |
A unified electrical SPICE model for piezoelectric transducers JM Gallière, P Papet, L Latorre 2007 IEEE International Behavioral Modeling and Simulation Workshop, 138-142, 2007 | 9 | 2007 |
Influence of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI Technology A Karel, M Comte, JM Galliere, F Azais, M Renovell IEEE Transactions on Nanotechnology 16 (3), 417-430, 2017 | 8 | 2017 |
Experimental characterization of an atmospheric environment with a stratospheric balloon F Wrobel, JR Vaille, D Pantel, L Dilillo, P Rech, JM Galliere, A Touboul, ... IEEE Transactions on Nuclear Science 58 (3), 945-951, 2011 | 8 | 2011 |
A complete analysis of the voltage behaviour of MOS transistor with Gate Oxide Short M Renovell, JM Gallière, F Azaïs, Y Bertrand Defect-Based Testing Work, 5-10, 2001 | 8 | 2001 |
Detectability challenges of bridge defects in finfet based logic cells F Forero, JM Galliere, M Renovell, V Champac Journal of Electronic Testing 34, 123-134, 2018 | 7 | 2018 |