Aleš Smrčka
Aleš Smrčka
Assistant professor of Computer Science, Brno University of Technology
Verified email at fit.vutbr.cz
Title
Cited by
Cited by
Year
Verifying parametrised hardware designs via counter automata
A Smrčka, T Vojnar
Haifa Verification Conference, 51-68, 2007
192007
Verifying concurrent programs using contracts
RJ Dias, C Ferreira, J Fiedor, JM Lourenço, A Smrcka, DG Sousa, ...
2017 IEEE International Conference on Software Testing, Verification and …, 2017
132017
Automatic formal correspondence checking of ISA and RTL microprocessor description
L Charvát, A Smrcka, T Vojnar
2012 13th International Workshop on Microprocessor Test and Verification …, 2012
102012
Using formal verification of parameterized systems in RAW hazard analysis in microprocessors
L Charvát, A Smrcka, T Vojnar
2014 15th International Microprocessor Test and Verification Workshop, 83-89, 2014
52014
Teoretická informatika: Studijní opora
M Češka, T Vojnar, A Smrčka, A Rogalewitz
Brno, FIT VUT v Brně, 2007
52007
Nástroj pro tvorbu obsahu databáze pro účely testování software
J Kotyz, A SMRČKA
Brno, CZ, 2018
42018
Advances in the ANaConDA framework for dynamic analysis and testing of concurrent C/C++ programs
J Fiedor, M Mužikovská, A Smrčka, O Vašíček, T Vojnar
Proceedings of the 27th ACM SIGSOFT International Symposium on Software …, 2018
22018
Hades: microprocessor hazard analysis via formal verification of parameterized systems
L Charvát, A Smrčka, T Vojnar
arXiv preprint arXiv:1612.04986, 2016
22016
Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems
L Charvát, A Smrčka, T Vojnar
International Conference on Computer Aided Systems Theory, 605-614, 2015
22015
Formal Verification of the CRC Algorithm Properties⋆
P Hlavka, A Smrčka, T Vojnar
22014
An Abstraction of Multi-port Memories with Arbitrary Addressable Units
L Charvát, A Smrčka, T Vojnar
International Conference on Computer Aided Systems Theory, 460-468, 2013
22013
Verifcation of Asynchronous and Parametrized Hardware Designs
A Smrcka
Information Sciences and Technologies Bulletin of the ACM Slovakia 2 (2), 60-69, 2010
22010
High-level modelling, analysis, and verification on FPGA-based hardware design
P Matoušek, A Smrčka, T Vojnar
Advanced Research Working Conference on Correct Hardware Design and …, 2005
22005
Generování modelů pro testy ze zdrojových kódů
PBD KRAUT, A SMRČKA
Diplomová práce, Vysoké učení technické v Brně, Fakulta informačních technologií, 2019
12019
Verifying VHDL designs with multiple clocks in SMV
A Smrčka, V Řehák, T Vojnar, D Šafránek, P Matoušek, Z Řehák
International Workshop on Parallel and Distributed Methods in Verification …, 2006
12006
Utilizing parametric systems for detection of pipeline hazards
L Charvát, A Smrčka, T Vojnar
International Journal on Software Tools for Technology Transfer, 1-28, 2020
2020
Verification of Asynchronous and Parametrized Hardware Designs: Monograph
A Smrčka, T Vojnar
Faculty of Information Technology, Brno University of Technology, 2010
2010
VHDL Design Verification Tools
Z Řehák, A Smrčka, J Holeček, D Šafránek, V Řehák
2009
Formal Verification of the CRC Algorithm Properties
A Smrčka, P Hlávka, D Šafránek, V Řehák, P Šimeček, T Vojnar
FIT BUT, 2006
2006
PROTOTYP INFORMAČNÍHO SYSTÉMU PRO EXE-KUTORSKÉ ÚŘADY
PBD BEZDĚK, A SMRČKA
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