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Saikat Chatterjee
Saikat Chatterjee
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A 65 nm standard cell library for ultra low-power applications
M Vohrmann, S Chatterjee, S Lütkemeier, T Jungeblut, M Porrmann, ...
2015 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015
112015
Aero: Design space exploration framework for resource-constrained cnn mapping on tile-based accelerators
S Yang, D Bhattacharjee, VBY Kumar, S Chatterjee, S De, P Debacker, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022
62022
Scaling down a level shifter circuit in 28 nm FDSOI technology
S Chatterjee, U Rückert
2018 Joint International EUROSOI Workshop and International Conference on …, 2018
52018
Resource Efficient Sub-VT Level Shifter Circuit Design Using a Hybrid Topology in 28 nm
S Chatterjee, U Rueckert
SMACD/PRIME 2021; International Conference on SMACD and 16th Conference on …, 2021
32021
Design of low-power digital circuits in the sub-threshold domain
S Chatterjee
2022
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Artikelen 1–5