Farnam Khalili Maybodi
Farnam Khalili Maybodi
University of Siena, University of Florence
Geverifieerd e-mailadres voor diism.unisi.it - Homepage
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AXIOM: A scalable, efficient and reconfigurable embedded platform
R Giorgi, M Procaccini, F Khalili
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 480-485, 2019
132019
A design space exploration tool set for future 1k-core high-performance computers
R Giorgi, M Procaccini, F Khalili
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and …, 2019
72019
Analyzing the impact of operating system activity of different linux distributions in a distributed environment
R Giorgi, M Procaccini, F Khalili
2019 27th Euromicro International Conference on Parallel, Distributed and …, 2019
62019
Energy efficiency exploration on the zynq ultrascale+
R Giorgi, F Khalili, M Procaccini
2018 30th International Conference on Microelectronics (ICM), 48-54, 2018
62018
Reconfigurable logic interface architecture for cpu-fpga accelerators
F Khalili, M Procaccini, R Giorgi
HiPEAC ACACES, 2018
52018
An FPGA-based Scalable Hardware Scheduler for Data-Flow Models
M Procaccini, F Khalili, R Giorgi
HiPEAC ACACES, 2018
22018
Translating Timing into an Architecture: the Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS)
MP Roberto Giorgi, Farnam Khalili
Hindawi - International Journal of Reconfigurable Computing, 24, 2019
1*2019
A Soft-IP for Performance Measuring of the Zynq Ultrascale+ CPU/FPGA interface
RG Farnam Khalili
http://www.dii.unisi.it/~giorgi/papers/Khalili19-acaces.pdf, 5-8, 2019
1*2019
A new two-path band pass Delta Sigma Modulator structure with tunability in filter resonance frequency
A Moradpour, F Khalili, EN Aghdam
2015 23rd Iranian Conference on Electrical Engineering, 1327-1331, 2015
12015
Center frequency and bandwidth tunable band pass delta sigma modulator
F Khalili, A Moradpour, EN Aghdam
2016 24th Iranian Conference on Electrical Engineering (ICEE), 704-708, 2016
2016
A Dynamic Load Balancer for a Cluster of FPGA SoCs
F Khalili, R Giorgi
An FPGA-Based Scalable Hardware Scheduler For Data-Flow Models
R Giorgi, M Procaccini, F Khalili
Translating Timing into an Architecture: the Synergy of COTSon and HLS
R Giorgi, F Khalili, M Procaccini
From COTSon to HLS: Translating Timing into an Architecture
R Giorgi, M Procaccini, F Khalili
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Artikelen 1–14