Charles Chiang
Charles Chiang
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Dummy filling technique for improved planarization of chip surface topography
S Sinha, J Luo, CC Chiang
US Patent 7,509,622, 2009
2382009
Design for Manufacturability and Yield for Nano-scale CMOS
C Chiang, J Kawa
Springer Science & Business Media, 2007
1552007
Method and system for facilitating floorplanning for 3D IC
S Sinha, CC Chiang
US Patent 8,006,212, 2011
1262011
Wirability of knock-knee layouts with 45 degrees wires
C Chiang, M Sarrafzadeh
IEEE Transactions on Circuits and Systems 38 (6), 613-624, 1991
1171991
Global routing based on Steiner min-max trees
C Chiang, M Sarrafzadeh, CK Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990
1041990
Machine-learning-based hotspot detection using topological classification and critical feature extraction
YT Yu, GH Lin, IHR Jiang, C Chiang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
972015
Simulating topography of a conductive material in a semiconductor wafer
J Luo, Q Su, C Chiang
US Patent 7,289,933, 2007
922007
Efficient process-hotspot detection using range pattern matching
H Yao, S Sinha, C Chiang, X Hong, Y Cai
2006 IEEE/ACM International Conference on Computer Aided Design, 625-632, 2006
812006
SAPOR: Second-order Arnoldi method for passive order reduction of RCS circuits
Y Su, J Wang, X Zeng, Z Bai, C Chiang, D Zhou
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
722004
Accurate process-hotspot detection using critical design rule extraction
YT Yu, YC Chan, S Sinha, IHR Jiang, C Chiang
Proceedings of the 49th Annual Design Automation Conference, 1167-1172, 2012
642012
Moving cast shadow detection by exploiting multiple cues
MT Yang, KH Lo, CC Chiang, WK Tai
IET Image Processing 2 (2), 95-104, 2008
632008
A powerful global router: based on Steiner min-max trees.
CC Chiang, M Sarrafzadeh, CK Wong
ICCAD, 2-5, 1989
571989
Identifying layout regions susceptible to fabrication issues by using range patterns
S Sinha, H Yao, CC Chiang
US Patent 7,503,029, 2009
542009
Accurate detection for process-hotspots with vias and incomplete specification
J Xu, S Sinha, CC Chiang
2007 IEEE/ACM International Conference on Computer-Aided Design, 839-846, 2007
542007
A weighted Steiner tree-based global router with simultaneous length and density minimization
C Chiang, CK Wong, M Sarrafzadeh
IEEE transactions on computer-aided design of integrated circuits and …, 1994
531994
The road to 3D EDA tool readiness
C Chiang, S Sinha
2009 Asia and South Pacific Design Automation Conference, 429-436, 2009
472009
A layout dependent full-chip copper electroplating topography model
J Luo, Q Su, C Chiang, J Kawa
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
442005
Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs
Q Chen, B Qiu, CC Chiang, X Hu, M Koshy, B Biswas
US Patent 8,146,032, 2012
382012
An IC manufacturing yield model considering intra-die variations
J Luo, S Sinha, Q Su, J Kawa, C Chiang
Proceedings of the 43rd annual Design Automation Conference, 749-754, 2006
352006
Range pattern definition of susceptibility of layout regions to fabrication issues
S Sinha, CC Chiang
US Patent 7,703,067, 2010
332010
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Artikelen 1–20