| YAGLE, a second generation functional abstractor for CMOS VLSI circuits A Lester, P Bazargan-Sabet, A Greiner Proceedings of the Tenth International Conference on Microelectronics (Cat …, 1998 | 20 | 1998 |
| A model for crosstalk noise evaluation in deep submicron processes PB Sabet, F Ilponse Proceedings of the IEEE 2001. 2nd International Symposium on Quality …, 2001 | 16 | 2001 |
| On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis D Fujimoto, N Miura, M Nagata, Y Hayashi, N Homma, Y Hori, T Katashita, ... 2013 International Symposium on Electromagnetic Compatibility, 405-410, 2013 | 13 | 2013 |
| Modeling crosstalk noise for deep submicron verification tools PB Sabet, F Ilponse Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 11 | 2001 |
| Smart security management in secure devices B Robisson, M Agoyan, P Soquet, S Le-Henaff, F Wajsbürt, ... Journal of Cryptographic Engineering 7, 47-61, 2017 | 10 | 2017 |
| Formal verification of timed VHDL programs A Bara, P Bazargan-Sabet, R Chevallier, E Encrenaz, D Ledu, P Renault 2010 Forum on Specification & Design Languages (FDL 2010), 1-6, 2010 | 9 | 2010 |
| A symbolic simulation approach in resolving signals' correlation J Dunoyer, N Abdallah, PB Sabet Proceedings of the 29th Annual Simulation Symposium, 203-211, 1996 | 8 | 1996 |
| A 29 Gops/Watt 3D-ready 16-core computing fabric with scalable cache coherent architecture using distributed L2 and adaptive L3 caches E Guthmuller, C Fuguet, P Vivet, C Bernard, I Miro-Panades, J Durupt, ... ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018 | 7 | 2018 |
| HyperFPGA: A possible general purpose reconfigurable hardware for custom supercomputing A Cicuttin, ML Crespo, KS Mannatunga, JG Samarawickrama, N Abdallah, ... 2016 International Conference on Advances in Electrical, Electronic and …, 2016 | 7 | 2016 |
| Methodology and development of a complete cad system for digital vlsi design PB Sabet, L Burgun, A Greiner, F Pétrot Proc. of the VIII Simposio Brasileiro de Concepcao de Circuitos Integrados …, 1994 | 7 | 1994 |
| Power grid redundant path contribution in system on chip (SoC) robustness against electromigration B Ouattara, L Doyen, D Ney, H Mehrez, P Bazargan-Sabet Microelectronics Reliability 54 (9-10), 1702-1706, 2014 | 5 | 2014 |
| Correlation power analysis using bit-level biased activity plaintexts against AES cores with countermeasures D Fujimoto, N Miura, M Nagata, Y Hayashi, N Homma, T Aoki, Y Hori, ... 2014 International Symposium on Electromagnetic Compatibility, Tokyo, 306-309, 2014 | 5 | 2014 |
| Modeling the effects of input slew rate and temporal proximity of input transitions in event-driven simulation N Abdallah, P Bazargan-Sabet 2006 Proceeding of the Thirty-Eighth Southeastern Symposium on System Theory …, 2006 | 5 | 2006 |
| An event-driven approach to crosstalk noise analysis [digital ICs] P Bazargan-Sabet, P Renault 36th Annual Simulation Symposium, 2003., 319-326, 2003 | 5 | 2003 |
| Efficient partitioning method for distributed logic simulation of VLSI circuits A Guettaf, P Bazargan-Sabet Proceedings 31st Annual Simulation Symposium, 196-201, 1998 | 5 | 1998 |
| Power noise measurements of cryptographic VLSI circuits regarding side-channel information leakage D Fujimoto, N Miura, M Nagata, Y Hayashi, N Homma, T Aoki, Y Hori, ... IEICE Transactions on Electronics 97 (4), 272-279, 2014 | 4 | 2014 |
| Redundancy Method to assess Electromigration Lifetime in power grid design B Ouattara, L Doyen, D Ney, H Mehrez, P Bazargan-Sabet, FL Bana 2013 IEEE International Interconnect Technology Conference-IITC, 1-3, 2013 | 4 | 2013 |
| A MoS Transistor Model for peak voltage calculation of crosstalk noise P Renault, P Bazargan-Sabet, D Le Dû 9th International Conference on Electronics, Circuits and Systems 2, 773-776, 2002 | 4 | 2002 |
| Management of the security in smart secure devices B Robisson, M Agoyan, S Bouquet, MH Nguyen, S Le Henaff, P Soquet, ... SSI 2010-Smart Systems Integration, 1-9, 2011 | 3 | 2011 |
| On the design of mixed-mode simulators for modern VLSI circuits N Abdallah, PB Sabet, A Greiner 38th Midwest Symposium on Circuits and Systems. Proceedings 2, 1168-1171, 1995 | 3 | 1995 |
