| Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV) X Liu, Q Chen, P Dixit, R Chatterjee, RR Tummala, SK Sitaraman 2009 59th Electronic components and technology conference, 624-629, 2009 | 216 | 2009 |
| Through-package-via formation and metallization of glass interposers V Sukumaran, Q Chen, F Liu, N Kumbhat, T Bandyopadhyay, H Chan, ... 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC …, 2010 | 143 | 2010 |
| Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias V Sukumaran, T Bandyopadhyay, Q Chen, N Kumbhat, F Liu, R Pucha, ... 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 583-588, 2011 | 94 | 2011 |
| Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test X Liu, Q Chen, V Sundaram, RR Tummala, SK Sitaraman Microelectronics Reliability 53 (1), 70-78, 2013 | 83 | 2013 |
| Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same V Sundaram, F Liu, R Tummala, V Sukumaran, V Sridharan, Q Chen US Patent 9,275,934, 2016 | 74 | 2016 |
| Trend from ICs to 3D ICs to 3D systems RR Tummala, V Sundaram, R Chatterjee, PM Raj, N Kumbhat, ... Custom Integrated Circuits Conference, 2009. CICC'09. IEEE, 439-444, 2009 | 68 | 2009 |
| Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC V Sundaram, Q Chen, Y Suzuki, G Kumar, F Liu, R Tummala 2012 IEEE 62nd Electronic Components and Technology Conference, 292-297, 2012 | 44 | 2012 |
| Through package via structures in panel-based silicon substrates and methods of making the same VV Sundaram, F Liu, RR Tummala, Q Chen US Patent App. 13/448,064, 2012 | 35 | 2012 |
| Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps X Liu, Q Chen, V Sundaram, M Simmons-Matthews, KP Wachtler, ... 2011 IEEE 61st electronic components and technology conference (ECTC), 1190-1195, 2011 | 34 | 2011 |
| Thermomechanical and electrochemical reliability of fine-pitch through-package-copper vias (TPV) in thin glass interposers and packages K Demir, K Ramachandran, Y Sato, Q Chen, V Sukumaran, R Pucha, ... 2013 IEEE 63rd Electronic Components and Technology Conference, 353-359, 2013 | 32 | 2013 |
| Reliability assessment of through-silicon vias in multi-die stack packages X Liu, Q Chen, V Sundaram, M Simmons-Matthews, KP Wachtler, ... IEEE Transactions on Device and Materials Reliability 12 (2), 263-271, 2012 | 30 | 2012 |
| Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs) Q Chen, T Bandyopadhyay, Y Suzuki, F Liu, V Sundaram, R Pucha, ... 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 855-860, 2011 | 28 | 2011 |
| Low cost, high performance, and high reliability 2.5 D silicon interposer V Sundaram, Q Chen, T Wang, H Lu, Y Suzuki, V Smet, M Kobayashi, ... 2013 IEEE 63rd Electronic Components and Technology Conference, 342-347, 2013 | 26 | 2013 |
| Enantioselective reduction of 3-substituted quinolines with a cyclopentadiene-based chiral Brønsted acid X Zhao, J Xiao, W Tang Synthesis 49 (14), 3157-3164, 2017 | 25 | 2017 |
| Modeling, Fabrication, and Characterization of Low-Cost and High-Performance Polycrystalline Panel-Based Silicon Interposer With Through Vias and Redistribution Layers Q Chen, Y Suzuki, G Kumar, V Sundaram, RR Tummala Components, Packaging and Manufacturing Technology, IEEE Transactions on 4 …, 2014 | 25 | 2014 |
| Demonstration of Through-Package-Vias in Panel-Based Polycrystalline Silicon Interposers for High Performance Q Chen High Reliability and Low Cost,” a Dissertation presented to the Academic …, 2015 | 21 | 2015 |
| Reliable design of electroplated copper through silicon vias X Liu, Q Chen, V Sundaram, S Muthukumar, RR Tummala, SK Sitaraman ASME International Mechanical Engineering Congress and Exposition 44281, 497-506, 2010 | 17 | 2010 |
| Double-Side Process and Reliability of Through-Silicon Vias (TSVs) for Passive Interposer Applications Q Chen, X Liu, V Sundaram, S Sitaraman, R Tummala Device and Materials Reliability, IEEE Transactions on 14 (4), 1041 - 1048, 2014 | 8 | 2014 |
| Study of Electromigration Failure in Solder Interconnects under Low Frequency Pulsed Direct Current Condition YR Kim, AT Osmanson, H Madanipou, CU Kim, PF Thompson, Q Chen 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 723-728, 2020 | 5 | 2020 |
| Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same V Sundaram, F Liu, RR Tummala, V Sukumaran, V Sridharan, Q Chen US Patent 10,672,718, 2020 | 5 | 2020 |
