Luca Sterpone
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Jaar
Microvesicles derived from adult human bone marrow and tissue specific mesenchymal stem cells shuttle selected pattern of miRNAs
F Collino, MC Deregibus, S Bruno, L Sterpone, G Aghemo, L Viltono, ...
PloS one 5 (7), e11803, 2010
6102010
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
FL Kastensmidt, L Sterpone, L Carro, MS Reorda
Design, Automation and Test in Europe, 1290-1295, 2005
2802005
A new reliability-oriented place and route algorithm for SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Computers 55 (6), 732-744, 2006
1812006
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Nuclear Science 52 (5), 1545-1549, 2005
1442005
A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Nuclear Science 54 (4), 965-970, 2007
1312007
A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs
L Sterpone, M Violante
IEEE Transactions on Nuclear Science 52 (6), 2217-2223, 2005
1132005
A new hardware/software platform and a new 1/E neutron source for soft error studies: Testing FPGAs at the ISIS facility
M Violante, L Sterpone, A Manuzzato, S Gerardin, P Rech, M Bagatin, ...
IEEE Transactions on Nuclear Science 54 (4), 1184-1189, 2007
1032007
On the evaluation of SEU sensitiveness in SRAM-based FPGAs
P Bernardi, MS Reorda, L Sterpone, M Violante
Proceedings. 10th IEEE International On-Line Testing Symposium, 115-120, 2004
712004
Simulation-based analysis of SEU effects in SRAM-based FPGAs
M Violante, L Sterpone, M Ceschia, D Bortolato, P Bernardi, MS Reorda, ...
IEEE Transactions on Nuclear Science 51 (6), 3354-3359, 2004
632004
Using benchmarks for radiation testing of microprocessors and FPGAs
H Quinn, WH Robinson, P Rech, M Aguirre, A Barnard, M Desogus, ...
IEEE Transactions on Nuclear Science 62 (6), 2547-2554, 2015
612015
Reconfigurable field programmable gate arrays for mission-critical applications
N Battezzati, L Sterpone, M Violante
Springer Science & Business Media, 2010
552010
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
F Abate, L Sterpone, CA Lisboa, L Carro, M Violante
IEEE Transactions on Nuclear Science 56 (4), 1992-2000, 2009
512009
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
MS Reorda, L Sterpone, M Violante
European Test Symposium (ETS'05), 136-141, 2005
502005
On the design of tunable fault tolerant circuits on sram-based fpgas for safety critical applications
L Sterpone, M Aguirre, J Tombs, H Guzman-Miranda
2008 Design, Automation and Test in Europe, 336-341, 2008
432008
Experimental validation of a tool for predicting the effects of soft errors in SRAM-based FPGAs
L Sterpone, M Violante, RH Sorensen, D Merodio, F Sturesson, ...
IEEE Transactions on Nuclear Science 54 (6), 2576-2583, 2007
432007
A novel fault tolerant and runtime reconfigurable platform for satellite payload processing
L Sterpone, M Porrmann, J Hagemeyer
IEEE transactions on computers 62 (8), 1508-1525, 2013
422013
An analysis based on fault injection of hardening techniques for SRAM-based FPGAs
L Sterpone, M Violante, S Rezgui
IEEE Transactions on Nuclear Science 53 (4), 2054-2059, 2006
422006
An error-detection and self-repairing method for dynamically and partially reconfigurable systems
MS Reorda, L Sterpone, A Ullah
IEEE Transactions on Computers 66 (6), 1022-1033, 2016
402016
Coping with the obsolescence of safety-or mission-critical embedded systems using FPGAs
H Guzman-Miranda, L Sterpone, M Violante, MA Aguirre, ...
IEEE Transactions on Industrial Electronics 58 (3), 814-821, 2010
392010
Analysis of SET propagation in flash-based FPGAs by means of electrical pulse injection
L Sterpone, N Battezzati, V Ferlet-Cavrois
IEEE Transactions on Nuclear Science 57 (4), 1820-1826, 2010
362010
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