| Method and apparatus for enhanced CMP planarization using surrounded dummy design HW Chen, HY Tsai, HC Chen, S Jeng, JH Lin, CT Lin, SH Hsu US Patent 7,235,424, 2007 | 188 | 2007 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... Electron Devices Meeting (IEDM), 2016 IEEE International, 2.7. 1-2.7. 4, 2016 | 175 | 2016 |
| 22 nm technology compatible fully functional 0.1 μm2 6T-SRAM cell BS Haran, A Kumar, L Adam, J Chang, V Basker, S Kanakasabapathy, ... International Electron Devices Meeting, 2008 | 96 | 2008 |
| Integration of EUV lithography in the fabrication of 22-nm node devices O Wood, CS Koay, K Petrillo, H Mizuno, S Raghunathan, J Arnold, ... SPIE, 2009 | 77 | 2009 |
| Polishing pad for a chemical mechanical polishing process HC Chen, TC Tsai US Patent 6,544,373, 2003 | 64 | 2003 |
| Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation CG Lou, HC Chen US Patent 5,872,045, 1999 | 64 | 1999 |
| Interconnect Performance and Scaling Strategy at 7 nm Node JHC Chen, TE Standaert, E Alptekin, TA Spooner, V Paruchuri International Interconnect Technology Conference, 2014 | 51 | 2014 |
| Freestanding spacer having sub-lithographic lateral dimension and method of forming same HC Chen, SC Fan, DK Kim, S Lian, FL LIE, L Jang US Patent App. 14/739,662, 2015 | 47 | 2015 |
| Double self aligned via patterning HC Chen, Y Xu, Y Yin, A Zhao US Patent App. 13/913,823, 2013 | 44 | 2013 |
| Insertion Strategy for EUV Lithography O Wood, J Arnold, T Brunner, M Burkhardt, JHC Chen SPIE, 2012 | 40 | 2012 |
| CVD Co and its Application to Cu Damascene Interconnections T Nogami, J Maniscalco, A Madan, P Flaitz, P DeHaven, C Parks, L Tai, ... International Interconnect Technology Conference, 2010 | 40 | 2010 |
| Double self aligned via patterning HC Chen, Y Xu, Y Yin, A Zhao US Patent 9,330,965, 2016 | 39 | 2016 |
| BEOL process integration for the 7 nm technology node T Standaert, G Beique, HC Chen, ST Chen, B Hamieh, J Lee, ... Interconnect Technology Conference/Advanced Metallization Conference (IITC …, 2016 | 37 | 2016 |
| Apparatus for controlling uniformity of polished material HC Chen, JY Wu, W Lur US Patent 6,093,089, 2000 | 37 | 2000 |
| Dual damascene process using selective W CVD CG Lou, HC Chen US Patent 6,110,826, 2000 | 36 | 2000 |
| High Reliability 32nmCu/ULK BEOL Based on PVD CuMn Seed, and its Extendibility T Nogami, T Bolom, A Simon, BY Kim, CK Hu, K Tsumura, A Madan, ... International Electron Devices Meeting, 2010 | 32 | 2010 |
| Multi-gate field-effect transistors with variable fin heights HC Chen, SC Fan, TE Standaert, CC Yeh US Patent App. 13/610,385, 2012 | 30 | 2012 |
| EUV lithography at the 22nm technology node O Wood, CS Koay, K Petrillo, H Mizuno, S Raghunathan, J Arnold, ... SPIE Advanced Lithography, 76361M-76361M-8, 2010 | 30 | 2010 |
| Metal electrical fuse structure HC Chen, HY Tsai, HW Chen, S Jeng, SY Hou US Patent 7,651,893, 2010 | 29 | 2010 |
| Physical vapor deposition device for forming a uniform metal layer on a semiconductor wafer HC Chen, JY Wu, W Lur US Patent 6,099,705, 2000 | 27 | 2000 |
