Jose Pineda de Gyvez
Jose Pineda de Gyvez
NXP Semiconductors and Eindhoven University of Technology
Verified email at tue.nl
Title
Cited by
Cited by
Year
A capacitor cross-coupled common-gate low-noise amplifier
W Zhuo, X Li, S Shekhar, SHK Embabi, JP de Gyvez, DJ Allstot, ...
IEEE transactions on circuits and systems II: Express briefs 52 (12), 875-879, 2005
3632005
Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design
W Zhuo, S Embabi, JP de Gyvez, E Sánchez-Sinencio
Proceedings of the 26th European Solid-State Circuits Conference, 77-80, 2000
1832000
Resistance characterization for weak open defects
RR Montañés, JP De Gyvez, P Volf
IEEE Design & Test of Computers 19 (5), 18-26, 2002
1652002
High sensitivity magnetic built-in current sensor
J De Wilde, JJP De Gyvez, FGM De Jong, JA Huisken, HMB Boeve, KP Le
US Patent 7,619,431, 2009
1172009
IC defect sensitivity for footprint-type spot defects
JP de Gyvez, C Di
IEEE transactions on computer-aided design of integrated circuits and …, 1992
1101992
An ultra-low-energy multi-standard JPEG co-processor in 65 nm CMOS with sub/near threshold supply voltage
Y Pu, JP De Gyvez, H Corporaal, Y Ha
IEEE Journal of Solid-State Circuits 45 (3), 668-680, 2010
1022010
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits
JP De Gyvez, HP Tuinhout
IEEE Journal of Solid-State Circuits 39 (1), 157-168, 2004
992004
Analog fault diagnosis based on ramping power supply current signature clusters
SAS Somayajula, E Sánchez-Sinencio, JP De Gyvez
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1996
761996
Color image processing in a cellular neural-network environment
CC Lee, JP de Gyvez
IEEE Transactions on neural networks 7 (5), 1086-1098, 1996
731996
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply
Y Pu, JP de Gyvez, H Corporaal, Y Ha
2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009
712009
Defect-oriented testing for nano-metric CMOS VLSI circuits
M Sachdev, JP De Gyvez
Springer Science & Business Media, 2007
642007
Lorenz-based chaotic cryptosystem: a monolithic implementation
OA Gonzales, G Han, JP De Gyvez, E Sánchez-Sinencio
IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2000
622000
Integrated circuit manufacturability: the art of process and design integration
JP de Gyvez, D Pradhan
Wiley-IEEE, 1999
51*1999
Programmable low noise amplifier with active-inductor load
W Zhuo, JP De Gyvez, E Sanchez-Sinencio
ISCAS'98. Proceedings of the 1998 IEEE International Symposium on Circuits …, 1998
511998
DNA computing based on chaos
G Manganaro, JP De Gyvez
Proceedings of 1997 IEEE International Conference on Evolutionary …, 1997
461997
Single-layer CNN simulator
CC Lee, JP De Gyvez
Proceedings of IEEE International Symposium on Circuits and Systems-ISCAS'94 …, 1994
441994
Built-in current sensor for/spl Delta/I/sub DDQ/testing
JR Vázquez, JP de Gyvez
IEEE Journal of Solid-State Circuits 39 (3), 511-518, 2004
432004
VDD ramp testing for RF circuits
JP de Gyvez, G Gronthoud, R Amine
ALQ 2 (R6), 6c, 2003
422003
Monitoring and controlling power consumption in a sequential logic circuit
JJP De Gyvez, JR Vazquez
US Patent 7,457,971, 2008
412008
Body-bias-driven design strategy for area-and performance-efficient CMOS circuits
M Meijer, JP de Gyvez
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (1), 42-51, 2010
382010
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