Cryo-CMOS circuits and systems for quantum computing applications B Patra, RM Incandela, JPG Van Dijk, HAR Homulle, L Song, ... IEEE Journal of Solid-State Circuits 53 (1), 309-321, 2017 | 395 | 2017 |
Cryo-CMOS for quantum computing E Charbon, F Sebastiano, A Vladimirescu, H Homulle, S Visser, L Song, ... 2016 IEEE International Electron Devices Meeting (IEDM), 13.5. 1-13.5. 4, 2016 | 205 | 2016 |
Characterization and compact modeling of nanometer CMOS transistors at deep-cryogenic temperatures RM Incandela, L Song, H Homulle, E Charbon, A Vladimirescu, ... IEEE Journal of the Electron Devices Society 6, 996-1006, 2018 | 193 | 2018 |
15.5 cryo-CMOS circuits and systems for scalable quantum computing E Charbon, F Sebastiano, M Babaie, A Vladimirescu, M Shahmohammadi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 264-265, 2017 | 69 | 2017 |
Cryo-CMOS electronic control for scalable quantum computing F Sebastiano, H Homulle, B Patra, R Incandela, J van Dijk, L Song, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 67 | 2017 |
The cryogenic temperature behavior of bipolar, MOS, and DTMOS transistors in standard CMOS H Homulle, L Song, E Charbon, F Sebastiano IEEE Journal of the Electron Devices Society 6, 263-270, 2018 | 54 | 2018 |
Stacked 3D RRAM array with graphene/CNT as edge electrodes Y Bai, H Wu, K Wang, R Wu, L Song, T Li, J Wang, Z Yu, H Qian Scientific reports 5 (1), 13785, 2015 | 53 | 2015 |
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures RM Incandela, L Song, HAR Homulle, F Sebastiano, E Charbon, ... 2017 47th European Solid-State Device Research Conference (ESSDERC), 58-61, 2017 | 36 | 2017 |
Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS L Song, H Homulle, E Charbon, F Sebastiano 2016 IEEE SENSORS, 1-3, 2016 | 18 | 2016 |
An efficient method for evaluating RRAM crossbar array performance L Song, J Zhang, A Chen, H Wu, H Qian, Z Yu Solid-State Electronics 120, 32-40, 2016 | 10 | 2016 |
Efficient models for designing GB-level 3-D 1S1R horizontal-stacked-RRAM and vertical-RRAM arrays L Song, J Zhang 2017 International Conference on Simulation of Semiconductor Processes and …, 2017 | 1 | 2017 |