Rabie Ben Atitallah
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A model-driven design framework for massively parallel embedded systems
A Gamatié, S Le Beux, É Piel, R Ben Atitallah, A Etien, P Marquet, ...
ACM Transactions on Embedded Computing Systems (TECS) 10 (4), 1-36, 2011
Path planning: A 2013 survey
PF Omar Souissi, Rabie Ben atitallah, David Duvivier, AbedlHakim Artiba ...
Industrial Engineering and Systems Management (IESM), Proceedings of 2013 …, 2013
Gaspard2: from MARTE to SystemC simulation
É Piel, RB Atitallah, P Marquet, S Meftali, S Niar, A Etien, JL Dekeyser, ...
proc. of the DATE 8, 2008
System-level power estimation tool for embedded processor based platforms
SK Rethinagiri, O Palomar, R Ben Atitallah, S Niar, O Unsal, ...
Proceedings of the 6th Workshop on Rapid Simulation and Performance …, 2014
Estimating energy consumption for an MPSoC architectural exploration
RB Atitallah, S Niar, A Greiner, S Meftali, JL Dekeyser
International Conference on Architecture of Computing Systems, 298-310, 2006
An MPSoC performance estimation framework using transaction level modeling
RB Atitallah, S Niar, S Meftali, JL Dekeyser
13th IEEE International Conference on Embedded and Real-Time Computing …, 2007
A model-driven approach for hybrid power estimation in embedded systems design
C Trabelsi, R Ben Atitallah, S Meftali, JL Dekeyser, A Jemai
EURASIP Journal on Embedded Systems 2011, 1-15, 2011
A model driven design framework for high performance embedded systems
A Gamatié, S Le Beux, É Piel, A Etien, RB Atitallah, P Marquet, ...
INRIA, 2008
MPSoC power estimation framework at transaction level modeling
RB Atitallah, S Niar, JL Dekeyser
2007 Internatonal Conference on Microelectronics, 245-248, 2007
Pets: Power and energy estimation tool at system-level
SK Rethinagiri, O Palomar, O Unsal, A Cristal, R Ben-Atitallah, S Niar
Fifteenth International Symposium on Quality Electronic Design, 535-542, 2014
An efficient framework for power-aware design of heterogeneous MPSoC
RB Atitallah, E Senn, D Chillet, M Lanoe, D Blouin
IEEE Transactions on Industrial Informatics 9 (1), 487-501, 2012
Multilevel MPSoC simulation using an MDE approach
RB Atitallah, E Piel, S Niar, P Marquet, JL Dekeyser
2007 IEEE International SOC Conference, 197-200, 2007
Hybrid system level power consumption estimation for fpga-based mpsoc
SK Rethinagiri, RB Atitallah, S Niar, E Senn, JL Dekeyser
2011 IEEE 29th International Conference on Computer Design (ICCD), 239-246, 2011
An efficient power estimation methodology for complex risc processor-based platforms
SK Rethinagiri, R Ben Atitallah, JL Dekeyser, E Senn, S Niar
Proceedings of the great lakes symposium on VLSI, 239-244, 2012
A system level power consumption estimation for MPSoC
SK Rethinagiri, RB Atitallah, JL Dekeyser
2011 International Symposium on System on Chip (SoC), 56-61, 2011
Using the uml profile for marte to mpsoc co-design
JL Dekeyser, A Gamatié, A Etien, RB Atitallah, P Boulet
First International Conference on Embedded Systems & Critical Applications …, 2008
Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays
A Ait El Cadi, O Souissi, R Ben Atitallah, N Belanger, A Artiba
Journal of Intelligent Manufacturing 29 (3), 629-640, 2018
Open-people: Open power and energy optimization PLatform and estimator
E Senn, D Chillet, O Zendra, C Belleudy, SB Bilavarn, RB Atitallah, ...
2012 15th Euromicro Conference on Digital System Design, 668-675, 2012
Multistage interconnection network for MPSoC: performances study and prototyping on FPGA
B Neji, Y Aydi, R Ben-atitallah, S Meftaly, M Abid, JL Dykeyser
2008 3rd International Design and Test Workshop, 11-16, 2008
Modèles et simulation des systèmes sur puce multiprocesseurs: estimation des performances et de la consommation d'énergie
R Ben Atitallah
Lille 1, 2008
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Articles 1–20