Davide Rossi
Davide Rossi
Associate Professor, University Of Bologna
Geverifieerd e-mailadres voor unibo.it
Geciteerd door
Geciteerd door
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
YodaNN: An architecture for ultralow power binary-weight CNN acceleration
R Andri, L Cavigelli, D Rossi, L Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
YodaNN: An ultra-low power convolutional neural network accelerator based on binary weights
R Andri, L Cavigelli, D Rossi, L Benini
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 236-241, 2016
GAP-8: A RISC-V SoC for AI at the Edge of the IoT
E Flamand, D Rossi, F Conti, I Loi, A Pullini, F Rotenberg, L Benini
2018 IEEE 29th International Conference on Application-specific Systems …, 2018
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ...
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
PULP: A parallel ultra low power platform for next generation IoT applications
D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015
Neurostream: Scalable and energy efficient deep learning with smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017
A transprecision floating-point platform for ultra-low power computing
G Tagliavini, S Mach, D Rossi, A Marongiu, L Benini
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors
A Garofalo, M Rusci, F Conti, D Rossi, L Benini
Philosophical Transactions of the Royal Society A 378 (2164), 20190155, 2020
Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing
A Pullini, D Rossi, I Loi, G Tagliavini, L Benini
IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019
PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision
F Conti, D Rossi, A Pullini, I Loi, L Benini
Journal of Signal Processing Systems 84, 339-354, 2016
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ...
Solid-State Electronics 117, 170-184, 2016
NEURAghe Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs
P Meloni, A Capotondi, G Deriu, M Brian, F Conti, D Rossi, L Raffo, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-24, 2018
A heterogeneous digital signal processor for dynamically reconfigurable computing
D Rossi, F Campi, S Spolzino, S Pucillo, R Guerrieri
IEEE Journal of Solid-State Circuits 45 (8), 1615-1626, 2010
Energy-efficient near-threshold parallel computing: The PULPv2 cluster
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ...
Ieee Micro 37 (5), 20-31, 2017
A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems
VJ Kartsch, S Benatti, PD Schiavone, D Rossi, L Benini
Information Fusion 43, 66-76, 2018
Power, area, and performance optimization of standard cell memory arrays through controlled placement
A Teman, D Rossi, P Meinerzhagen, L Benini, A Burg
ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (4 …, 2016
PULP-HD: Accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform
F Montagna, A Rahimi, S Benatti, D Rossi, L Benini
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
Design and evaluation of a processing-in-memory architecture for the smart memory cube
E Azarkhish, D Rossi, I Loi, L Benini
Architecture of Computing Systems–ARCS 2016: 29th International Conference …, 2016
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