| Semiconductor device and method of manufacturing the same M Kawano, K Soejima, N Takahashi, Y Kurita, M Komuro, S Matsui US Patent App. 11/602,346, 2007 | 139 | 2007 |
| A 3D stacked memory integrated on a logic device using SMAFTI technology Y Kurita, S Matsui, N Takahashi, K Soejima, M Komuro, M Itou, ... 2007 Proceedings 57th Electronic Components and Technology Conference, 821-829, 2007 | 124 | 2007 |
| A 3D packaging technology for 4 Gbit stacked DRAM with 3 Gbps data transfer M Kawano, S Uchiyama, Y Egawa, N Takahashi, Y Kurita, K Soejima, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 113 | 2006 |
| Semiconductor device comprising through-electrode interconnect M Kawano US Patent 7,541,677, 2009 | 104 | 2009 |
| Three-dimensional packaging technology for stacked DRAM with 3-Gb/s data transfer M Kawano, N Takahashi, Y Kurita, K Soejima, M Komuro, S Matsui IEEE Transactions on Electron Devices 55 (7), 1614-1620, 2008 | 100 | 2008 |
| Electronic device and method of manufacturing the same Y Kurita, M Kawano, K Soejima US Patent 8,354,340, 2013 | 60 | 2013 |
| System in wafer-level package technology with RDL-first process N Motohashi, T Kimura, K Mineo, Y Yamada, T Nishiyama, K Shibuya, ... 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 59-64, 2011 | 57 | 2011 |
| A novel" SMAFTI" package for inter-chip wide-band data transfer Y Kurita, K Soejima, K Kikuchi, M Takahashi, M Tago, M Koike, L Shibuya, ... 56th Electronic Components and Technology Conference 2006, 9 pp., 2006 | 55 | 2006 |
| Semiconductor device and semiconductor module employing thereof S Matsui, M Kawano US Patent 7,768,133, 2010 | 54 | 2010 |
| Vertical integration of stacked DRAM and high-speed logic device using SMAFTI technology Y Kurita, S Matsui, N Takahashi, K Soejima, M Komuro, M Itou, M Kawano IEEE transactions on advanced packaging 32 (3), 657-665, 2009 | 53 | 2009 |
| Offset-bonded, multi-chip semiconductor device M Kawano, S Matsui US Patent 7,145,247, 2006 | 49 | 2006 |
| Fan-Out Wafer-Level Packaging with highly flexible design capabilities Y Kurita, T Kimura, K Shibuya, H Kobayashi, F Kawashiro, N Motohashi, ... 3rd Electronics System Integration Technology Conference ESTC, 1-6, 2010 | 48 | 2010 |
| Method for manufacturing semiconductor device K Soejima, M Kawano US Patent 7,528,068, 2009 | 48 | 2009 |
| Semiconductor device and method of manufacturing the same M Kawano, K Soejima, Y Kurita US Patent 7,800,233, 2010 | 43 | 2010 |
| Semiconductor device and method for manufacturing the same K Mori, H Murai, S Yamamichi, M Kawano, K Soejima US Patent 8,304,915, 2012 | 41 | 2012 |
| Semiconductor device with plate-shaped component M Kawano, N Takahashi US Patent 8,143,716, 2012 | 41 | 2012 |
| Semiconductor device and method for manufacturing same M Kawano, K Soejima, N Takahashi US Patent 7,633,167, 2009 | 38 | 2009 |
| Development of 3D-packaging process technology for stacked memory chips T Mitsuhashi, Y Egawa, O Kato, Y Saeki, H Kikuchi, S Uchiyama, ... MRS Online Proceedings Library (OPL) 970, 0970-Y03-06, 2006 | 38 | 2006 |
| Wafer-to-Wafer Hybrid Bonding Development by Advanced Finite Element Modeling for 3-D IC Packages L Ji, FX Che, HM Ji, HY Li, M Kawano IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …, 2020 | 36 | 2020 |
| Semiconductor element-embedded wiring substrate S Yamamichi, H Murai, K Mori, K Kikuchi, Y Nakashima, M Kawano, ... US Patent App. 13/040,021, 2011 | 35 | 2011 |
Yoichiro KuritaTokyo Institute of Technology在 m.titech.ac.jp 的电子邮件经过验证
