| EazyHTM: Eager-lazy hardware transactional memory S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ... Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 158 | 2009 |
| Wear leveling of a memory array TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ... US Patent 9,857,986, 2018 | 72 | 2018 |
| Cooperative data deduplication in a solid state storage array TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic US Patent 10,013,169, 2018 | 68 | 2018 |
| Cooperative data deduplication in a solid state storage array TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic US Patent 10,013,169, 2018 | 68 | 2018 |
| Metadata hardening and parity accumulation for log-structured arrays I Koltsidas, CJ Camp, N Ioannou, RA Pletka, AK Kourtis, S Tomic, ... US Patent 10,437,670, 2019 | 44 | 2019 |
| Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management CJ Camp, TJ Fisher, AD Fry, N Ioannou, R Pletka, S Tomic US Patent 9,563,373, 2017 | 36 | 2017 |
| Facing target assembly and sputter deposition apparatus C Koh, SH Sawasaki, J Shi, YR Cheng US Patent 6,689,253, 2004 | 36* | 2004 |
| Vertical sub-micron CMOS transistors on (110),(111),(311),(511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same L Forbes, W Noble, A Reinberg US Patent App. 10/222,997, 2004 | 34 | 2004 |
| Multi-lug socket tool L Boston US Patent 6,668,685, 2003 | 33* | 2003 |
| Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ... US Patent 9,251,909, 2016 | 30 | 2016 |
| Characterization and analysis of bit errors in 3D TLC NAND flash memory N Papandreou, H Pozidis, T Parnell, N Ioannou, R Pletka, S Tomic, ... 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019 | 29 | 2019 |
| The velox transactional memory stack P Felber, E Riviere, WM Moreira, D Harmanci, P Marlier, S Diestelhorst, ... Micro, IEEE 30 (5), 76-87, 2010 | 27* | 2010 |
| Increasing storage efficiency of a data protection technique RA Pletka, RI Stoica, I Koltsidas, N Ioannou, S Tomic, AK Kourtis, ... US Patent 10,592,173, 2020 | 26 | 2020 |
| Non-volatile memory controller cache architecture with support for separation of data streams CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic, ... US Patent 9,779,021, 2017 | 26 | 2017 |
| Reducing unnecessary calibration of a memory unit for which the error count margin has been exceeded N Ioannou, N Papandreou, RA Pletka, S Tomic US Patent 10,824,352, 2020 | 25 | 2020 |
| Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic US Patent 9,632,927, 2017 | 24 | 2017 |
| Non-volatile memory system having an increased effective number of supported heat levels CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic US Patent 10,078,582, 2018 | 23* | 2018 |
| Techniques for dynamically adjusting over-provisioning space of a flash controller based on workload characteristics CJ Camp, TJ Fisher, AD Fry, N Ioannou, T Parnell, RA Pletka, S Tomic US Patent 10,592,110, 2020 | 20 | 2020 |
| A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory E Akpinar, S Tomić, A Cristal, O Unsal, V Mateo TRANSACT, 2011 | 19 | 2011 |
| Threshold voltage shifting at a lower bit error rate by intelligently performing dummy configuration reads N Ioannou, N Papandreou, RA Pletka, S Tomic US Patent 10,170,195, 2019 | 18 | 2019 |
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