Vincenzo Catania
Vincenzo Catania
Verified email at dieei.unict.it
Title
Cited by
Cited by
Year
Multi-objective mapping for mesh-based NoC architectures
G Ascia, V Catania, M Palesi
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004
2872004
Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip
G Ascia, V Catania, M Palesi, D Patti
IEEE Transactions on Computers 57 (6), 809-820, 2008
2642008
Noxim: An open, extensible and cycle-accurate network on chip simulator
V Catania, A Mineo, S Monteleone, M Palesi, D Patti
2015 IEEE 26th international conference on application-specific systems …, 2015
2202015
Application specific routing algorithms for networks on chip
M Palesi, R Holsmark, S Kumar, V Catania
IEEE Transactions on Parallel and Distributed Systems 20 (3), 316-330, 2008
2102008
Cycle-accurate network on chip simulation with noxim
V Catania, A Mineo, S Monteleone, M Palesi, D Patti
ACM Transactions on Modeling and Computer Simulation (TOMACS) 27 (1), 1-25, 2016
1882016
An approch for monitoring and smart planning of urban solid waste management using smart-M3 platform
V Catania, D Ventura
Proceedings of 15th conference of open innovations association FRUCT, 24-31, 2014
1292014
A methodology for design of application specific deadlock-free routing algorithms for NoC systems
V Catania, R Holsmark, S Kumar, M Palesi
Proceedings of the 4th International Conference on Hardware/Software …, 2006
1222006
Efficient design space exploration for application specific systems-on-a-chip
G Ascia, V Catania, AG Di Nuovo, M Palesi, D Patti
Journal of Systems Architecture 53 (10), 733-750, 2007
1162007
A comparative analysis of fuzzy versus conventional policing mechanisms for ATM networks
V Catania, G Ficili, S Palazzo, D Panno
IEEE/ACM Transactions on networking 4 (3), 449-459, 1996
1051996
Data encoding schemes in networks on chip
M Palesi, G Ascia, F Fazzino, V Catania
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
922011
VLSI hardware architecture for complex fuzzy systems
G Ascia, V Catania, M Russo
IEEE Transactions on Fuzzy Systems 7 (5), 553-570, 1999
861999
A GA-based design space exploration framework for parameterized system-on-a-chip platforms
G Ascia, V Catania, M Palesi
IEEE Transactions on Evolutionary Computation 8 (4), 329-346, 2004
782004
A VLSI fuzzy inference processor based on a discrete analog approach
V Catania, A Puliafito, M Russo, L Vita
IEEE Transactions on Fuzzy Systems 2 (2), 93-106, 1994
741994
A VLSI fuzzy expert system for real-time traffic control in ATM networks
G Ascia, V Catania, G Ficili, S Palazzo, D Panno
IEEE Transactions on fuzzy systems 5 (1), 20-31, 1997
671997
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip.
G Ascia, V Catania, M Palesi
J. Univers. Comput. Sci. 12 (4), 370-394, 2006
622006
Using fuzzy logic in ATM source traffic control: Lessons and perspectives
V Catania, G Ficili, S Palazzo, D Panno
IEEE Communications Magazine 34 (11), 70-74, 1996
551996
Mapping cores on network-on-chip
G Ascia, V Catania, M Palesi
International Journal of Computational Intelligence Research 1 (1), 109-126, 2005
542005
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration.
G Ascia, V Catania, M Palesi, D Patti
ESTImedia, 65-72, 2003
532003
Neighbors-on-path: A new selection strategy for on-chip networks
G Ascia, V Catania, M Palesi, D Patti
2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, 79-84, 2006
502006
Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip
M Palesi, S Kumar, V Catania
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
452010
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