| Smart traffic control system with application of image processing techniques MM Hasan, G Saha, A Hoque, MB Majumder 2014 International Conference on Informatics, Electronics & Vision (ICIEV), 1-4, 2014 | 70 | 2014 |
| Robustness analysis of a memristive crossbar PUF against modeling attacks M Uddin, MB Majumder, GS Rose IEEE Transactions on Nanotechnology 16 (3), 396-405, 2017 | 69 | 2017 |
| Techniques for improved reliability in memristive crossbar PUF circuits M Uddin, MB Majumder, GS Rose, K Beckmann, H Manem, Z Alamgir, ... 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 212-217, 2016 | 41 | 2016 |
| Chaos computing for mitigating side channel attack B Majumder, S Hasan, M Uddin, GS Rose 2018 IEEE international symposium on hardware oriented security and trust …, 2018 | 33 | 2018 |
| Physically unclonable and reconfigurable computing system (purcs) for hardware security applications AS Shanta, MB Majumder, MS Hasan, GS Rose IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 28 | 2020 |
| Design considerations for memristive crossbar physical unclonable functions M Uddin, MDB Majumder, K Beckmann, H Manem, Z Alamgir, NC Cady, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 1-23, 2017 | 28 | 2017 |
| Memristor crossbar PUF based lightweight hardware security for IoT M Uddin, AS Shanta, MB Majumder, MS Hasan, GS Rose 2019 IEEE International Conference on Consumer Electronics (ICCE), 1-4, 2019 | 20 | 2019 |
| Design of a reconfigurable chaos gate with enhanced functionality space in 65nm cmos AS Shanta, MB Majumder, MS Hasan, M Uddin, GS Rose 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 18 | 2018 |
| A chaos-based complex micro-instruction set for mitigating instruction reverse engineering MS Hasan, MB Majumder, AS Shanta, M Uddin, GS Rose Journal of Hardware and Systems Security 4, 69-85, 2020 | 14 | 2020 |
| Sneak path enabled authentication for memristive crossbar memories MB Majumder, M Uddin, GS Rose, J Rajendran 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 1-6, 2016 | 13 | 2016 |
| Practical realisation of a return map immune Lorenz‐based chaotic stream cipher in circuitry D Brown, A Hedayatipour, MB Majumder, GS Rose, N McFarlane, ... IET Computers & Digital Techniques 12 (6), 297-305, 2018 | 12 | 2018 |
| Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map MS Hasan, AS Shanta, PS Paul, M Sadia, MB Majumder, GS Rose 2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS), 1-5, 2020 | 10 | 2020 |
| Design of a lightweight reconfigurable prng using three transistor chaotic map AS Shanta, MS Hasan, MB Majumder, GS Rose 2019 IEEE 62nd international midwest symposium on circuits and systems …, 2019 | 9 | 2019 |
| Nanoelectronic security designs for resource-constrained internet of things devices: Finding security solutions with nanoelectronic hardwares M Uddin, B Majumder, GS Rose IEEE Consumer Electronics Magazine 7 (6), 15-22, 2018 | 8 | 2018 |
| A designer's rationale for nanoelectronic hardware security primitives GS Rose, M Uddin, MB Majumder 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 194-199, 2016 | 7 | 2016 |
| Sensitivity analysis of nanowire biosensor in the partially depleted and fully depleted mode of subthreshold region MB Majumder, MZ Alvi, MR Islam, M Najmussadat, R Islam Sensing and bio-sensing research 7, 55-61, 2016 | 7 | 2016 |
| Design for eliminating operation specific power signatures from digital logic MB Majumder, MS Hasan, A Shanta, M Uddin, G Rose Proceedings of the 2019 on Great Lakes Symposium on VLSI, 111-116, 2019 | 5 | 2019 |
| A secure integrity checking system for nanoelectronic resistive ram MB Majumder, MS Hasan, M Uddin, GS Rose IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (2), 416-429, 2018 | 5 | 2018 |
| Exploiting memristive crossbar memories as dual-Use security primitives in IoT devices GS Rose, MB Majumder, M Uddin 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 615-620, 2017 | 5 | 2017 |
| Evaluation, optimization, and enhancement of chaos based reconfigurable logic design MS Hasan, MB Majumder, AS Shanta, M Uddin, GS Rose 2019 SoutheastCon, 1-6, 2019 | 3 | 2019 |
Garrett S. RoseProfessor, University of TennesseeVerified email at utk.edu
