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Thomas Canhao Xu 许粲昊
Thomas Canhao Xu 许粲昊
Beijing Normal University-Hong Kong Baptist University United International College (UIC)
Verified email at suda.edu.cn - Homepage
Title
Cited by
Cited by
Year
A study of through silicon via impact to 3D network-on-chip design
TC Xu, P Liljeberg, H Tenhunen
2010 International Conference on Electronics and Information Engineering 1 …, 2010
622010
A study of 3d network-on-chip design for data parallel h. 264 coding
TC Xu, AW Yin, P Liljeberg, H Tenhunen
Microprocessors and Microsystems 35 (7), 603-612, 2011
462011
Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip
TC Xu, P Liljeberg, H Tenhunen
14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011
462011
A generic adaptive path-based routing method for MPSoCs
M Daneshtalab, M Ebrahimi, TC Xu, P Liljeberg, H Tenhunen
Journal of Systems Architecture 57 (1), 109-120, 2011
442011
Sound insulation properties in low-density, mechanically strong and ductile nanoporous polyurea aerogels
S Malakooti, HG Churu, A Lee, T Xu, H Luo, N Xiang, C Sotiriou-Leventis, ...
Journal of Non-Crystalline Solids 476, 36-45, 2017
432017
Optimal placement of vertical connections in 3D network-on-chip
TC Xu, G Schley, P Liljeberg, M Radetzki, J Plosila, H Tenhunen
Journal of Systems Architecture 59 (7), 441-454, 2013
382013
Tree-model based mapping for energy-efficient and low-latency network-on-chip
B Yang, TC Xu, T Säntti, J Plosila
13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010
372010
Explorations of honeycomb topologies for network-on-chip
AW Yin, TC Xu, P Liljeberg, H Tenhunen
2009 Sixth IFIP International Conference on Network and Parallel Computing …, 2009
372009
Numerical implementation of a bounding surface plasticity model for sand under high strain-rate loadings in LS-DYNA
TH Xu, LM Zhang
Computers and Geotechnics 66, 203-218, 2015
312015
Multi-application multi-step mapping method for many-core network-on-chips
B Yang, L Guang, TC Xu, AW Yin, T Säntti, J Plosila
NORCHIP 2010, 1-6, 2010
262010
Mixed-criticality run-time task mapping for noc-based many-core systems
M Fattah, AM Rahmani, TC Xu, A Kanduri, P Liljeberg, J Plosila, ...
2014 22nd Euromicro international conference on parallel, distributed, and …, 2014
252014
Optimal memory controller placement for chip multiprocessor
TC Xu, P Liljeberg, H Tenhunen
2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on …, 2011
252011
Fluorescent digital image correlation techniques in experimental mechanics
ZX Hu, TG Xu, XM Wang, ZM Xie, HY Luo, Y He, L Guo, YP Li, RZ Gan, ...
Science China Technological Sciences 61, 21-36, 2018
212018
A high-efficiency low-cost heterogeneous 3d network-on-chip design
TC Xu, P Liljeberg, J Plosila, H Tenhunen
Proceedings of the Fifth International Workshop on Network on Chip …, 2012
172012
Exploration of heuristic scheduling algorithms for 3d multicore processors
TC Xu, P Liljeberg, J Plosila, H Tenhunen
Proceedings of the 15th International Workshop on Software and Compilers for …, 2012
142012
An Optimized Network-on-Chip Design for Data Parallel FFT1
TC Xu, P Liljeberg, H Tenhunen
Procedia Engineering 30, 311-318, 2012
132012
Evaluation of the effect of thermal oxidation and moisture on the interfacial shear strength of unidirectional IM7/BMI composite by fiber push-in nanoindentation
T Xu, H Luo, Z Xu, Z Hu, M Minary-Jolandan, S Roy, H Lu
Experimental Mechanics 58, 111-123, 2018
122018
Explorations of optimal core and cache placements for chip multiprocessor
TC Xu, P Liljeberg, H Tenhunen
2011 NORCHIP, 1-6, 2011
122011
Evaluate and optimize parallel barnes-hut algorithm for emerging many-core architectures
TC Xu, P Liljeberg, J Plosila, H Tenhunen
2013 International Conference on High Performance Computing & Simulation …, 2013
112013
An analysis of designing 2d/3d chip multiprocessor wit different cache architecture
TC Xu, L Guang, AW Yin, B Yang, P Liljeberg, H Tenhunen
NORCHIP 2010, 1-6, 2010
102010
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