| OpenPiton+ Ariane: The first open-source, SMP Linux-booting RISC-V system scaling from one to many cores J Balkind, K Lim, F Gao, J Tu, D Wentzlaff, M Schaffner, F Zaruba, L Benini Workshop on Computer Architecture Research with RISC-V (CARRV), 1-6, 2019 | 46 | 2019 |
| OpenPiton at 5: A nexus for open and agile hardware design J Balkind, TJ Chang, PJ Jackson, G Tziantzioulis, A Li, F Gao, A Lavrov, ... IEEE Micro 40 (4), 22-31, 2020 | 17 | 2020 |
| DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 5 | 2023 |
| Exploring efficient strategies for minesweeper J Tu, T Li, S Chen, C Zu, Z Gu Workshops at the Thirty-First AAAI Conference on Artificial Intelligence, 2017 | 4 | 2017 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 2 | 2023 |
| OPDB: A Scalable and Modular Design Benchmark G Tziantzioulis, TJ Chang, J Balkind, J Tu, F Gao, D Wentzlaff IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 2 | 2021 |
