Hung-Yi Liu
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On learning-based methods for design-space exploration with high-level synthesis
HY Liu, LP Carloni
Proceedings of the 50th annual design automation conference, 1-7, 2013
1482013
Voltage island aware floorplanning for power and timing optimization
WP Lee, HY Liu, YW Chang
2006 IEEE/ACM International Conference on Computer Aided Design, 389-394, 2006
912006
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning
WP Lee, HY Liu, YW Chang
2007 IEEE/ACM International Conference on Computer-Aided Design, 650-655, 2007
652007
Compositional system-level design exploration with planning of high-level synthesis
HY Liu, M Petracca, LP Carloni
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 641-646, 2012
492012
A provably good approximation algorithm for power optimization using multiple supply voltages
HY Liu, WP Lee, YW Chang
Proceedings of the 44th Annual Design Automation Conference, 887-890, 2007
302007
A synthesis-parameter tuning system for autonomous design-space exploration
MM Ziegler, HY Liu, G Gristede, B Owens, R Nigaglioni, LP Carloni
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
192016
Supervised design space exploration by compositional approximation of Pareto sets
HY Liu, I Diakonikolas, M Petracca, L Carloni
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 399-404, 2011
182011
Voltage-island partitioning and floorplanning under timing constraints
WP Lee, HY Liu, YW Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
182009
Current path analysis for electrostatic discharge protection
HY Liu, CW Lin, SJ Chou, WT Tu, CH Liu, YW Chang, SY Kuo
2006 IEEE/ACM International Conference on Computer Aided Design, 510-515, 2006
112006
Scalable auto-tuning of synthesis parameters for optimizing high-performance processors
MM Ziegler, HY Liu, LP Carloni
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
102016
An efficient graph-based algorithm for ESD current path analysis
CH Liu, HY Liu, CW Lin, SJ Chou, YW Chang, SY Kuo, SY Yuan, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
92008
A method to abstract RTL IP blocks into C++ code and enable high-level synthesis
N Bombieri, HY Liu, F Fummi, L Carloni
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-9, 2013
72013
Sensitivity-based multiple-Vt cell swapping for leakage power reduction
WP Lee, HY Liu, KH Ho, YW Chang
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI …, 2008
32008
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
LIU Hung-Yi, MM Ziegler
US Patent 10,083,268, 2018
22018
METRICS 2.0: A Machine-Learning Based Optimization System for IC Design
S Hashemi, CT Ho, AB Kahng, HY Liu, S Reda
Workshop on Open-Source EDA Technology, 21, 2018
22018
Enhanced parameter tuning for very-large-scale integration synthesis
LIU Hung-Yi, MM Ziegler
US Patent 9,619,602, 2017
22017
Scheduling simultaneous optimization of multiple very-large-scale-integration designs
LIU Hung-Yi, MM Ziegler
US Patent 9,600,623, 2017
22017
SynTunSys: A Synthesis Parameter Autotuning System for Optimizing High-Performance Processors
MM Ziegler, HY Liu, G Gristede, B Owens, R Nigaglioni, J Kwon, ...
Machine Learning in VLSI Computer-Aided Design, 539-570, 2019
12019
A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs.
MM Ziegler, HY Liu, G Gristede, B Owens, R Nigaglioni, LP Carloni
RES4ANT@ DATE, 8-12, 2016
12016
Enhanced parameter tuning for very-large-scale integration synthesis
LIU Hung-Yi, MM Ziegler
US Patent 10,002,221, 2018
2018
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