Dominique Borrione
Dominique Borrione
Retired Professor from UGA, Grenoble
Verified email at
Cited by
Cited by
Proven correct monitors from PSL specifications
K Morin-Allory, D Borrione
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
CONLAN report
R Piloty, M Barbacci, D Borrione, D Dietmeyer
Springer Science & Business Media, 1983
Formal verification of VHDL descriptions in the Prevail environment
DD Borrione, LV Pierre, AM Salem
IEEE Design & Test of Computers 9 (2), 42-56, 1992
A method for symbolic verification of synchronous circuits
T Filkorn
Computer Hardware Description Languages and their Applications, 249-259, 1991
A generic model for formally verifying NoC communication architectures: A case study
D Borrione, A Helmy, L Pierre, J Schmaltz
First International Symposium on Networks-on-Chip (NOCS'07), 127-136, 2007
Design error diagnosis in sequential circuits
A Wahba, D Borrione
Advanced Research Working Conference on Correct Hardware Design and …, 1995
The Conlan project: concepts, implementations, and applications
R Piloty
Computer 18 (02), 81-92, 1985
A method for automatic design error location and correction in combinational logic circuits
AM Wahba, D Borrione
Journal of Electronic Testing 8, 113-127, 1996
A formal approach to the verification of networks on chip
D Borrione, A Helmy, L Pierre, J Schmaltz
EURASIP Journal on Embedded Systems 2009, 1-14, 2009
CONLAN: a formal construction method for hardware description languages: basic principles
R Piloty, M Barbacci, D Borrione, D Dietmeyer, F Hill, P Skelly
Proceedings of the May 19-22, 1980, national computer conference, 209-217, 1980
PSL-based online monitoring of digital systems
D Borrione, M Liu, P Ostier, L Fesquet
Applications of Specification and Design Languages for SoCs: Selected papers …, 2006
A functional formalization of on chip communications
J Schmaltz, D Borrione
Formal Aspects of Computing 20, 241-258, 2008
Semantics of a verification-oriented subset of VHDL
D Déharbe, D Borrione
Advanced Research Working Conference on Correct Hardware Design and …, 1995
Towards a formal theory of on chip communications in the ACL2 logic
J Schmaltz, D Borrione
Proceedings of the sixth international workshop on the ACL2 theorem prover …, 2006
On-line assertion-based verification with proven correct monitors
D Borrione, M Liu, K Morin-Allory, P Ostier, L Fesquet
2005 International Conference on Information and Communication Technology …, 2005
A generic network on chip model
J Schmaltz, D Borrione
International Conference on Theorem Proving in Higher Order Logics, 310-325, 2005
A functional approach to the formal specification of networks on chip
J Schmaltz, D Borrione
International Conference on Formal Methods in Computer-Aided Design, 52-66, 2004
An approach to the introduction of formal validation in an asynchronous circuit design flow
D Borrione, M Boubekeur, E Dumitrescu, M Renaudin, JB Rigaud, ...
36th Annual Hawaii International Conference on System Sciences, 2003 …, 2003
A compositional model for the functional verification of high-level synthesis results
D Borrione, J Dushina, L Pierre
IEEE transactions on very large scale integration (VLSI) systems 8 (5), 526-530, 2000
PREVAIL: A proof environment for VHDL descriptions
D Borrione, L Pierre, A Salem
Correct-Hardware-Design-Methodologies.-Proceedings-of-the-Advanced-Research …, 1992
The system can't perform the operation now. Try again later.
Articles 1–20