Fernando Gehm Moraes
Fernando Gehm Moraes
Professor at the School of Technology at PUCRS
Geverifieerd e-mailadres voor pucrs.br - Homepage
Geciteerd door
Geciteerd door
HERMES: an infrastructure for low area overhead packet-switching networks on chip
F Moraes, N Calazans, A Mello, L Möller, L Ost
Integration 38 (1), 69-93, 2004
Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs
E Carvalho, N Calazans, F Moraes
RSP, Rapid System Prototyping, 34-40, 2007
Dynamic task mapping for MPSoCs
EL de Souza Carvalho, NLV Calazans, FG Moraes
IEEE Design & Test of Computers 27 (5), 26-35, 2010
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
A Mello, L Tedesco, N Calazans, F Moraes
SBCCI - Symposium on Integrated Circuits and System Design, 178-183, 2005
HeMPS-a framework for NoC-based MPSoC generation
EA Carara, RP de Oliveira, NLV Calazans, FG Moraes
ISCAS, IEEE International Symposium on Circuits and Systems, 1345-1348, 2009
A scalable test strategy for network-on-chip routers
AM Amory, E Brião, É Cota, M Lubaszewski, FG Moraes
ITC, IEEE International Test Conference, 2005
Exploring NoC mapping strategies: an energy and timing aware technique
C Marcon, N Calazans, F Moraes, A Susin, I Reis, F Hessel
DATE, Design, Automation and Test in Europe, 502-507, 2005
MAIA: a framework for networks on chip generation and verification
L Ost, A Mello, J Palma, F Moraes, N Calazans
ASP-DAC, Asia and South Pacific Design Automation Conference, 49-52, 2005
Congestion-aware task mapping in heterogeneous MPSoCs
E Carvalho, F Moraes
SOC, International Symposium on System-on-Chip, 1-4, 2008
Remote and Partial Reconfiguration of FPGAs: tools and trends
D Mesquita, F Moraes, J Palma, L Moller, N Calazans
RAW, Parallel and Distributed Processing Symposium, 8 pp., 2003
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses
NLV Calazans, FG Moraes
IEEE Transactions on Education 44 (2), 109-119, 2001
Evaluation of routing algorithms on mesh based nocs
AV de Mello, LC Ost, FG Moraes, NLV Calazans
PUCRS, Av. Ipiranga 22, 2004
Comparison of network-on-chip mapping algorithms targeting low energy consumption
CAM Marcon, EI Moreno, NLV Calazans, FG Moraes
IET Computers & Digital Techniques 2 (6), 471-482, 2008
Distributed Resource Management in NoC-Based MPSoCs with Dynamic Cluster Sizes
G Castilhos, M Mandelli, G Madalozzo, F Moraes
ISVLSI - IEEE Computer Society Annual Symposium on VLSI, 2013
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping
FG Moraes, A Mello, L Möller, L Ost, NLV Calazans
VLSI-SOC - IFIP/IEEE International Conference on Very Large Scale …, 2003
Traffic generation and performance evaluation for mesh-based NoCs
L Tedesco, A Mello, D Garibotti, N Calazans, F Moraes
SBCCI, Symposium on Integrated Circuits and System Design, 184-189, 2005
From VHDL register transfer level to SystemC transaction level modeling: a comparative case study
N Calazans, E Moreno, F Hessel, V Rosa, F Moraes, E Carara
SBCCI, Symposium on Integrated Circuits and System Design, 355-360, 2003
Topology-Agnostic Fault-Tolerant NoC Routing Method
E Wachter, A Erichsen, A Amory, F Moraes
DATE - Design, Automation & Test in Europe, 1595-1600, 2013
NoC power estimation at the RTL abstraction level
G Guindani, C Reinbrecht, T Raupp, N Calazans, FG Moraes
ISVLSI, IEEE Computer Society Annual Symposium on VLSI, 475-478, 2008
Core Communication Interface for FPGAs
JC Palma, AV de Mello, L Moller, F Moraes, N Calazans
SBCCI - Symposium on Integrated Circuits and Systems Design, 183-188, 2002
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