Vojtech Rehak
Vojtech Rehak
Masaryk university, Faculty of Informatics
Verified email at fi.muni.cz
Cited by
Cited by
LTL to Büchi Automata Translation: Fast and More Deterministic
T Babiak, M Křetínský, V Řehák, J Strejček
TACAS 2012: 18th International Conference on Tools and Algorithms for the …, 2012
Extended process rewrite systems: Expressiveness and reachability
M Křetínský, V Řehák, J Strejček
CONCUR 2004-Concurrency Theory, 355-370, 2004
Stochastic real-time games with qualitative timed automata objectives
T Brázdil, J Krčál, J Křetínský, A Kučera, V Řehák
CONCUR 2010-Concurrency Theory, 207-221, 2011
Verification of open interactive Markov chains
T Brázdil, H Hermanns, J Krcál, J Kretinsky, V Rehák
FSTTSC 2012 18, 2012
Fixed-delay Events in Generalized Semi-Markov Processes Revisited
T Brázdil, J Krčál, J Křetínský, V Řehák
CONCUR 2011-Concurrency Theory: 22nd International Conference, 140-155, 2011
Optimizing performance of continuous-time stochastic systems using timeout synthesis
T Brázdil, Ľ Korenčiak, J Krčál, P Novotný, V Řehák
International Conference on Quantitative Evaluation of Systems, 141-159, 2015
On decidability of LTL model checking for process rewrite systems
L Bozzelli, M Křetínský, V Řehák, J Strejček
Acta informatica 46 (1), 1-28, 2009
Reachability of Hennessy-Milner properties for weakly extended PRS
M Křetínský, V Řehák, J Strejček
FSTTCS 2005: Foundations of Software Technology and Theoretical Computer …, 2005
Measuring performance of continuous-time stochastic processes using timed automata
T Brázdil, J Krcál, J Kretínský, A Kucera, V Řehák
Proceedings of the 14th international conference on Hybrid systems …, 2011
Model checking in IPv6 Hardware Router Design
J Barnat, T Brázdil, P Krčál, V Řehák, D Šafránek
CESNET technical report 8, 2002
Verification of COMBO6 VHDL Design
T Kratochvíla, V Řehák, P Šimeček
Technical report, 2003
Verification results in Liberouter project
J Holeček, T Kratochvíla, V Řehák, D Šafránek, P Šimeček
Technická zpráva CESNET, 2004
Hardware Router’s Lookup Machine and its Formal Verification
D Antoš, V Řehák, J Kořenek
ICN’2004 Conference Proceedings 2, 2004
Solving adversarial patrolling games with bounded error
M Abaffy, T Brázdil, V Rehák, B Bosanský, A Kucera, J Krcál
AAMAS, 1617-1618, 2014
Verification process of hardware design in liberouter project
J Holeček, T Kratochvíla, V Řehák, D Šafránek, P Šimeček
Technická Zpráva 5, 2004
Packet header matching in Combo6 IPv6 router
D Antoš, J Kořenek, K Minaříková, V Řehák
CESNET, zspo, 2003
Dealing with zero density using piecewise phase-type approximation
L Korenčiak, J Krčál, V Řehák
European Workshop on Performance Engineering, 119-134, 2014
How to formalize fpga hardware design
J Holecek, T Kratochvıla, V Rehák, D Šafránek, P Simecek
Technical Report 4/2004, CESNET, 2004
Solving patrolling problems in the internet environment
T Brázdil, A Kučera, V Řehák
Proceedings of the 27th International Joint Conference on Artificial …, 2018
Sequence chart studio
M Bezdeka, O Bouda, L Korenciak, M Madzin, V Reh'k
2012 12th International Conference on Application of Concurrency to System …, 2012
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