| Power-efficient combinatorial optimization using intrinsic noise in memristor Hopfield neural networks F Cai, S Kumar, T Van Vaerenbergh, X Sheng, R Liu, C Li, Z Liu, M Foltin, ... Nature Electronics 3 (7), 409-418, 2020 | 254 | 2020 |
| A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018 | 250 | 2018 |
| XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks X Sun, S Yin, X Peng, R Liu, J Seo, S Yu 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 230 | 2018 |
| 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019 | 224 | 2019 |
| Ultra-low-energy three-dimensional oxide-based electronic synapses for implementation of robust high-accuracy neuromorphic computation systems B Gao, Y Bi, HY Chen, R Liu, P Huang, B Chen, L Liu, X Liu, S Yu, ... ACS nano 8 (7), 6998-7004, 2014 | 193 | 2014 |
| Spatiotemporal information processing emulated by multiterminal neuro‐transistor networks Y He, S Nie, R Liu, S Jiang, Y Shi, Q Wan Advanced Materials 31 (21), 1900903, 2019 | 168 | 2019 |
| A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ... IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019 | 153 | 2019 |
| Experimental characterization of physical unclonable function based on 1 kb resistive random access memory arrays R Liu, H Wu, Y Pang, H Qian, S Yu IEEE Electron Device Letters 36 (12), 1380-1383, 2015 | 135 | 2015 |
| A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors X Si, WS Khwa, JJ Chen, JF Li, X Sun, R Liu, S Yu, H Yamauchi, Q Li, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11), 4172-4185, 2019 | 127 | 2019 |
| Parallelizing SRAM arrays with customized bit-cell for binary neural networks R Liu, X Peng, X Sun, WS Khwa, X Si, JJ Chen, JF Li, MF Chang, S Yu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 112 | 2018 |
| Fully parallel RRAM synaptic array for implementing binary neural network with (+ 1,− 1) weights and (+ 1, 0) neurons X Sun, X Peng, PY Chen, R Liu, J Seo, S Yu 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 574-579, 2018 | 104 | 2018 |
| Optimizing weight mapping and data flow for convolutional neural networks on RRAM based processing-in-memory architecture X Peng, R Liu, S Yu 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 81 | 2019 |
| Physical unclonable function exploiting sneak paths in resistive cross-point array L Gao, PY Chen, R Liu, S Yu IEEE Transactions on Electron Devices 63 (8), 3109-3115, 2016 | 71 | 2016 |
| Optimizing weight mapping and data flow for convolutional neural networks on processing-in-memory architectures X Peng, R Liu, S Yu IEEE Transactions on Circuits and Systems I: Regular Papers 67 (4), 1333-1343, 2019 | 65 | 2019 |
| Analytic model of endurance degradation and its practical applications for operation scheme optimization in metal oxide based RRAM P Huang, B Chen, YJ Wang, FF Zhang, L Shen, R Liu, L Zeng, G Du, ... 2013 IEEE International electron devices meeting, 22.5. 1-22.5. 4, 2013 | 65 | 2013 |
| Exploiting resistive cross-point array for compact design of physical unclonable function PY Chen, R Fang, R Liu, C Chakrabarti, Y Cao, S Yu 2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015 | 60 | 2015 |
| A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation R Liu, H Wu, Y Pang, H Qian, S Yu 2016 IEEE international symposium on hardware oriented security and trust …, 2016 | 58 | 2016 |
| Recent progress on emerging transistor‐based neuromorphic devices Y He, L Zhu, Y Zhu, C Chen, S Jiang, R Liu, Y Shi, Q Wan Advanced Intelligent Systems 3 (7), 2000210, 2021 | 57 | 2021 |
| IGZO-based floating-gate synaptic transistors for neuromorphic computing Y He, R Liu, S Jiang, C Chen, L Zhu, Y Shi, Q Wan Journal of Physics D: Applied Physics 53 (21), 215106, 2020 | 56 | 2020 |
| Optimization of RRAM-based physical unclonable function with a novel differential read-out method Y Pang, H Wu, B Gao, N Deng, D Wu, R Liu, S Yu, A Chen, H Qian IEEE Electron Device Letters 38 (2), 168-171, 2017 | 56 | 2017 |
Shimeng YuGeorgia Institute of Technology, Professor of ECEGeverifieerd e-mailadres voor ece.gatech.edu
