| A 0.6 V 54DB SNR analog frontend with 0.18% THD for low power sensory applications in 65NM CMOS K Badami, KD Murthy, P Harpe, M Verhelst 2018 IEEE Symposium on VLSI Circuits, 241-242, 2018 | 10 | 2018 |
| Measuring internal signals of an integrated circuit KD Murthy, M Parmar, P Tadeparthy, M Venkateswaran US Patent 10,459,030, 2019 | 2 | 2019 |
| Load current sensing at low output voltage B Ramachandran, KD Murthy, AD Saha US Patent 11,243,235, 2022 | 1 | 2022 |
| Input current extraction from inductor current in a voltage converter KD Murthy, V Gakhar, M Venkateswaran, P Tadeparthy US Patent 10,177,644, 2019 | 1 | 2019 |
| Power switch reverse current protection systems KD Murthy, S Roy, DK Jain, AG Godbole US Patent App. 17/514,968, 2022 | | 2022 |
| Short detect scheme for an output pin B Ramachandran, KD Murthy US Patent 10,838,016, 2020 | | 2020 |
| Single circuit one-time programmable memory and volatile memory A Borah, M Venkateswaran, KD Murthy, V Gakhar, P Tadeparthy US Patent 10,297,334, 2019 | | 2019 |
| Matrix methods for finding NA Jain, KD Murthy, Hamsapriye International Journal of Mathematical Education in Science and Technology 45 …, 2014 | | 2014 |
Komail BadamiCSEMVerified email at csem.ch
