Phillip Christie
Phillip Christie
Verified email at imec.be
Title
Cited by
Cited by
Year
The interpretation and application of Rent's rule
P Christie, D Stroobandt
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (6), 639-648, 2000
3102000
The interpretation and application of Rent's rule
P Christie, D Stroobandt
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (6), 639-648, 2000
2992000
Analog and digital circuit design in 65 nm CMOS: End of the road?
G Gielen, W Dehaene
Design, Automation and Test in Europe, 37-42, 2005
812005
The analytical form of the length distribution function for computer interconnection
JE Cotter, P Christie
IEEE transactions on circuits and systems 38 (3), 317-320, 1991
401991
High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD
J Mitard, L Witters, MG Bardon, P Christie, J Franco, A Mercha, ...
2010 International Electron Devices Meeting, 10.6. 1-10.6. 4, 2010
392010
A fractal analysis of interconnection complexity
P Christie
Proceedings of the IEEE 81 (10), 1492-1499, 1993
371993
First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling
T Merelle, G Curatola, A Nackaerts, N Collaert, MJH Van Dal, G Doornbos, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
302008
Comparison of silicon ring modulators with interdigitated and lateral PN junctions
M Pantouvaki, H Yu, M Rakowski, P Christie, P Verheyen, G Lepage, ...
IEEE Journal of Selected Topics in Quantum Electronics 19 (2), 7900308-7900308, 2012
292012
A differential equation for placement analysis
P Christie
IEEE transactions on very large scale integration (VLSI) systems 9 (6), 913-921, 2001
242001
Demonstration of an extendable and industrial 300mm BEOL integration for the 65-nm technology node
O Hinsinger, R Fox, E Sabouret, C Goldberg, C Verove, W Besling, P Brun, ...
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004
232004
Prelayout interconnect yield prediction
P Christie, JP de Gyvez
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (1), 55-59, 2003
172003
Prelayout interconnect yield prediction
P Christie, JP de Gyvez
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (1), 55-59, 2003
172003
Pre-layout prediction of interconnect manufacturability
P Christie, J Pineda de Gyvez
Proceedings of the 2001 international workshop on System-level interconnect …, 2001
172001
Rent exponent prediction methods
P Christie
IEEE transactions on very large scale integration (VLSI) systems 8 (6), 679-688, 2000
162000
Stochastic wire length sampling for cycle time estimation
M Iqbal, A Sharkawy, U Hameed, P Christie
Proceedings of the 2002 international workshop on System-level interconnect …, 2002
152002
Multi-objective optimization of interconnect geometry
RA Wildman, JI Kramer, DS Weile, P Christie
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (1), 15-23, 2003
142003
Si1-xGex-channel PFETs: Scalability, layout considerations and compatibility with other stress techniques
G Eneman, G Hellings, J Mitard, L Witters, S Yamaguchi, MG Bardon, ...
ECS Transactions 35 (3), 493, 2011
132011
An analysis of the effect of wire resistance on circuit level performance at the 45-nm technology node
VH Nguyen, P Christie, A Heringa, A Kumar, R Ng
Proceedings of the IEEE 2005 International Interconnect Technology …, 2005
132005
The impact of back-end-of-line process variations on critical path timing
VN Hoang, A Kumar, P Christie
2006 International Interconnect Technology Conference, 193-195, 2006
122006
Balancing resistance and capacitance of signal interconnects for power saving
VN Hoang, G Doornbos, J Michelon, A Kumar, A Nackaerts, P Christie
2007 IEEE International Interconnect Technology Conferencee, 126-128, 2007
112007
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