| Qubits made by advanced semiconductor manufacturing AMJ Zwerver, T Krähenmann, TF Watson, L Lampert, HC George, ... arXiv preprint arXiv:2101.12650, 2021 | 215 | 2021 |
| Quantum computing assemblies AA Elsherbini, JA Falcon, HC George, SM Liff, JS Clarke US Patent 10,380,496, 2019 | 84 | 2019 |
| Quantum well stacks for quantum dot devices P Amin, NK Thomas, JS Clarke, JM Torres, R Pillarisetty, HC George, ... US Patent 10,763,347, 2020 | 68 | 2020 |
| Double-sided quantum dot devices R Pillarisetty, JM Roberts, NK Thomas, HC George, JS Clarke US Patent App. 16/323,682, 2019 | 60 | 2019 |
| Quantum Transport Properties of Industrial D Sabbagh, N Thomas, J Torres, R Pillarisetty, P Amin, HC George, ... Physical Review Applied 12 (1), 014013, 2019 | 57 | 2019 |
| Quantum circuit assemblies with triaxial cables L Lampert, R Pillarisetty, NK Thomas, HC George, JM Roberts, ... US Patent 10,565,515, 2020 | 56 | 2020 |
| Gate arrangements in quantum dot devices NK Thomas, JS Clarke, W Rachmady, R Pillarisetty, HC George, K Singh, ... US Patent 10,490,727, 2019 | 46 | 2019 |
| Vertical flux bias lines coupled to vertical squid loops in superconducting qubits R Caudillo, L Lampert, DJ Michalak, JM Roberts, R Pillarisetty, ... US Patent App. 16/102,780, 2019 | 45 | 2019 |
| Quantum dot devices HC George, R Pillarisetty, JM Roberts, NK Thomas, JS Clarke US Patent App. 16/314,788, 2019 | 44 | 2019 |
| Fin strain in quantum dot devices R Pillarisetty, K Singh, PH Keys, R Caudillo, HC George, ZR Yoscovits, ... US Patent 10,665,770, 2020 | 42 | 2020 |
| Quantum circuit assemblies with Josephson junctions utilizing resistive switching materials ZR Yoscovits, R Caudillo, R Pillarisetty, HC George, AA Elsherbini, ... US Patent 10,803,396, 2020 | 36 | 2020 |
| Single electron transistors (sets) and set-based qubit-detector arrangements HC George, JS Clarke US Patent App. 16/329,706, 2019 | 35 | 2019 |
| High Volume Electrical Characterization of Semiconductor Qubits R Pillarisetty, HC George, TF Watson, L Lampert, N Thomas, S Bojarski, ... 2019 IEEE International Electron Devices Meeting (IEDM), 31.5. 1-31.5. 4, 2019 | 32 | 2019 |
| Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology R Pillarisetty, N Thomas, HC George, K Singh, J Roberts, L Lampert, ... 2018 IEEE International Electron Devices Meeting (IEDM), 6.3. 1-6.3. 4, 2018 | 32 | 2018 |
| Reducing crosstalk from flux bias lines in qubit devices L Lampert, AA Elsherbini, JS Clarke, JM Roberts, R Pillarisetty, ... US Patent 10,847,705, 2020 | 27 | 2020 |
| Experimental demonstration of hybrid CMOS-single electron transistor circuits AA Prager, HC George, AO Orlov, GL Snider Journal of Vacuum Science & Technology B, Nanotechnology and …, 2011 | 25 | 2011 |
| Quantum circuit assemblies with at least partially buried transmission lines and capacitors HC George, AA Elsherbini, L Lampert, JS Clarke, R Pillarisetty, ... US Patent App. 16/012,815, 2019 | 24 | 2019 |
| Metal-insulator-metal single electron transistors with tunnel barriers prepared by atomic layer deposition G Karbasian, M McConnell, H George, L Schneider, M Filmer, A Orlov, ... Applied Sciences 7 (3), 246, 2017 | 23 | 2017 |
| Quantum circuit assemblies with vertically-stacked parallel-plate capacitors R Caudillo, ZR Yoscovits, L Lampert, DJ Michalak, JM Roberts, ... US Patent 10,665,769, 2020 | 21 | 2020 |
| Sidewall metal spacers for forming metal gates in quantum devices HC George, ZR Yoscovits, NK Thomas, L Lampert, JS Clarke, JM Roberts, ... US Patent App. 15/891,518, 2019 | 20 | 2019 |
Ravi PillarisettyIntel CorporationVerified email at intel.com
