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Erik Jan Marinissen
Erik Jan Marinissen
Scientific Director at imec
Geverifieerd e-mailadres voor imec.be - Homepage
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Testing embedded-core based system chips
Y Zorian, EJ Marinissen, S Dey
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
8211998
Test wrapper and test access mechanism co-optimization for system-on-chip
V Iyengar, K Chakrabarty, EJ Marinissen
Journal of Electronic Testing 18, 213-230, 2002
4942002
A structured and scalable mechanism for test access to embedded reusable cores
EJ Marinissen, R Arendsen, G Bos, H Dingemanse, M Lousberg, ...
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
4531998
A set of benchmarks for modular testing of SOCs
EJ Marinissen, V Iyengar, K Chakrabarty
Proceedings. International Test Conference, 519-528, 2002
4082002
Testing 3D chips containing through-silicon vias
EJ Marinissen, Y Zorian
2009 International Test Conference, 1-11, 2009
4002009
Wrapper design for embedded core test
EJ Marinissen, SK Goel, M Lousberg
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
3462000
Scan chain design for test time reduction in core-based ICs
J Aerts, EJ Marinissen
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
2771998
On using rectangle packing for SOC wrapper/TAM co-optimization
V Iyengar, K Chakrabarty, EJ Marinissen
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 253-258, 2002
2342002
Effective and efficient test architecture design for SOCs
SK Goel, EJ Marinissen
Proceedings. International Test Conference, 529-538, 2002
2332002
Towards a standard for embedded core test: An example
EJ Marinissen, Y Zorian, R Kapur, T Taylor, L Whetsel
International Test Conference 1999. Proceedings (IEEE Cat. No. 99CH37034 …, 1999
2161999
A structured and scalable test access architecture for TSV-based 3D stacked ICs
EJ Marinissen, J Verbree, M Konijnenburg
2010 28th VLSI Test Symposium (VTS), 269-274, 2010
1992010
On IEEE P1500’s standard for embedded core test
EJ Marinissen, R Kapur, M Lousberg, T McLaurin, M Ricchetti, Y Zorian, ...
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 1-19, 2002
1882002
Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip
K Chakrabarty, EJ Marinissen
IEEE Transactions on Computers 52 (12), 1619-1632, 2003
1652003
Challenges in embedded memory design and test
EJ Marinissen, B Prince, D Keltel-Schulz, Y Zorian
Design, Automation and Test in Europe, 722-727, 2005
1332005
Challenges and emerging solutions in testing TSV-based 2 1 over 2D-and 3D-stacked ICs
EJ Marinissen
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012
1302012
Application of deterministic logic BIST on industrial circuits
G Kiefer, H Vranken, E Jan Marinissen, HJ Wunderlich
Journal of Electronic Testing 17, 351-362, 2001
1292001
SOC test architecture design for efficient utilization of test bandwidth
SK Goel, EJ Marinissen
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003
1282003
Testing TSV-based three-dimensional stacked ICs
EJ Marinissen
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1262010
Impact of 3D design choices on manufacturing cost
D Velenis, M Stucchi, EJ Marinissen, B Swinnen, E Beyne
2009 IEEE International Conference on 3D System Integration, 1-5, 2009
1242009
Efficient wrapper/TAM co-optimization for large SOCs
V Iyengar, K Chakrabarty, EJ Marinissen
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
1172002
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Artikelen 1–20