| Efficient function approximation using truncated multipliers and squarers EG Walters, MJ Schulte Computer Arithmetic, 2005. ARITH-17 2005. 17th IEEE Symposium on, 232-239, 2005 | 79 | 2005 |
| Design alternatives for barrel shifters MR Pillmeier, MJ Schulte, EG Walters Advanced Signal Processing Algorithms, Architectures, and Implementations …, 2002 | 70 | 2002 |
| Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs EG Walters Computers 5 (4), 20, 2016 | 53 | 2016 |
| Truncated squarers with constant and variable correction EG Walters, MJ Schulte, MG Arnold Advanced Signal Processing Algorithms, Architectures, and Implementations …, 2004 | 26 | 2004 |
| Techniques and devices for performing arithmetic EG Walters III US Patent App. 15/025,770, 2016 | 20 | 2016 |
| Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs EG Walters Signals, Systems and Computers, 2014 48th Asilomar Conference on, 1247-1251, 2014 | 20 | 2014 |
| Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations M Sadeghian, JE Stine, EG Walters Electronics 5 (2), 17, 2016 | 18 | 2016 |
| Using truncated multipliers in DCT and IDCT hardware accelerators EG Walters, MG Arnold, MJ Schulte Advanced Signal Processing Algorithms, Architectures, and Implementations …, 2003 | 18 | 2003 |
| Combined multiplication and sum-of-squares units MJ Schulte, L Marquette, S Krithivasan, EG Walters, J Glossner Application-Specific Systems, Architectures, and Processors, 2003 …, 2003 | 17 | 2003 |
| Combined unsigned and two's complement hybrid squarers EG Walters, J Schlessman, MJ Schulte Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth …, 2001 | 17 | 2001 |
| Design tradeoffs using truncated multipliers in FIR filter implementations EG Walters, MJ Schulte Advanced Signal Processing Algorithms, Architectures, and Implementations …, 2002 | 16 | 2002 |
| Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs EG Walters Electronics 6 (4), 101, 2017 | 14 | 2017 |
| Linear and quadratic interpolators using truncated-matrix multipliers and squarers EG Walters III Computers 4 (4), 293-321, 2015 | 10 | 2015 |
| Fast, bit-accurate simulation of truncated-matrix multipliers and squarers EG Walters, MJ Schulte Signals, Systems and Computers (ASILOMAR), 2010 Conference Record of the …, 2010 | 9 | 2010 |
| 24-bit significand multiplier for FPGA floating-point multiplication EG Walters Signals, Systems and Computers, 2015 49th Asilomar Conference on, 717-721, 2015 | 8 | 2015 |
| Optimized cubic chebyshev interpolator for elementary function hardware implementations M Sadeghian, JE Stine, EG Walters Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, 1536-1539, 2014 | 6 | 2014 |
| Automatic VHDL model generation of parameterized FIR filters EG Walters III, J Glossner, MJ Schulte Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation, 1, 2003 | 6 | 2003 |
| Software Architecture and Framework for Programmable Logic Controllers: A Case Study and Suggestions for Research EG Walters, EJ Bryla Machines 4 (2), 13, 2016 | 5 | 2016 |
| Using truncated-matrix multipliers and squarers in high-performance DSP systems EG Walters III Lehigh University, 2009 | 2 | 2009 |
| Reducing Hearing Aid Power Consumption Using Truncated-Matrix Multipliers TL Hemminger, EG Walters Global Journal of Research In Engineering, 2013 | 1 | 2013 |
Michael SchulteAdvanced Micro DevicesGeverifieerd e-mailadres voor amd.com
