| Test synthesis with alternative graphs R Ubar IEEE Design & Test of Computers 13 (1), 48-57, 1996 | 206 | 1996 |
| Design and test technology for dependable systems-on-chip R Ubar, J Raik, HT Vierhaus IGI global, 2011 | 200 | 2011 |
| Test generation for digital circuits using alternative graphs R Ubar Proc. Tallinn Technical University 409, 75-81, 1976 | 98 | 1976 |
| Fast test pattern generation for sequential circuits using decision diagram representations J Raik, R Ubar Journal of Electronic Testing 16, 213-226, 2000 | 73 | 2000 |
| Multi-valued simulation of digital circuits with structurally synthesized binary decision diagrams R Ubar Multiple Valued Logic 4, 141-157, 1998 | 66 | 1998 |
| An external test approach for network-on-a-chip switches J Raik, V Govind, R Ubar 2006 15th Asian Test Symposium, 437-442, 2006 | 64 | 2006 |
| Test configurations for diagnosing faulty links in NoC switches J Raik, R Ubar, V Govind 12th IEEE European Test Symposium (ETS'07), 29-34, 2007 | 57 | 2007 |
| Test cost minimization for hybrid BIST G Jervan, Z Peng, R Ubar Proceedings IEEE International Symposium on Defect and Fault Tolerance in …, 2000 | 56 | 2000 |
| Test time minimization for hybrid BIST of core-based systems Jervan, Eles, Peng, Ubar, Jenihhin 2003 Test Symposium, 318-323, 2003 | 51 | 2003 |
| Parallel X-fault simulation with critical path tracing technique R Ubar, S Devadze, J Raik, A Jutman 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 49 | 2010 |
| Turbo Tester: a CAD system for teaching digital test G Jervan, A Markus, P Paomets, J Raik, R Ubar Microelectronics Education: Proceedings of the 2 nd European Workshop held …, 1998 | 48 | 1998 |
| A hybrid BIST architecture and its optimization for SoC testing G Jervan, Z Peng, R Ubar, H Kruus Proceedings International Symposium on Quality Electronic Design, 273-279, 2002 | 43 | 2002 |
| SSBDDs: Advantageous model and efficient algorithms for digital circuit modeling, simulation & test A Jutman, J Raik, R Ubar Proc. of 5th International Workshop on Boolean Problems (IWSBP'02), 19-20, 2002 | 42 | 2002 |
| Testing strategies for networks on chip R Ubar, J Raik Networks on chip, 131-152, 2003 | 41 | 2003 |
| Back-tracing and event-driven techniques in high-level simulation with decision diagrams R Ubar, J Raik, A Morawiec 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 208-211, 2000 | 37 | 2000 |
| Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips J Raik, V Govind, R Ubar IET computers & digital techniques 3 (5), 476-486, 2009 | 36 | 2009 |
| Feasibility of structurally synthesized BDD models for test generation J Raik, R Ubar Proc. of the IEEE European Test Workshop, 145-146, 1998 | 35 | 1998 |
| Defect-oriented fault simulation and test generation in digital circuits W Kuzmicz, W Pleskacz, J Raik, R Ubar Proceedings of the IEEE 2001. 2nd International Symposium on Quality …, 2001 | 33 | 2001 |
| Sequential circuit test generation using decision diagram models J Raik, R Ubar Proceedings of the conference on Design, automation and test in Europe, 145-es, 1999 | 33 | 1999 |
| Turbo Tester–diagnostic package for research and training M Aarna, E Ivask, A Jutman, E Orasson, J Raik, R Ubar, V Vislogubov, ... Радиоэлектроника и информатика, 69-73, 2003 | 32 | 2003 |
Jaan RaikTallinn University of TechnologyVerified email at taltech.ee
