| 3-Gb/s high-speed true random number generator using common-mode operating comparator and sampling uncertainty of D flip-flop SG Bae, Y Kim, Y Park, C Kim IEEE Journal of Solid-State Circuits 52 (2), 605-610, 2016 | 54 | 2016 |
| A scalable bandwidth mismatch calibration technique for time-interleaved ADCs Y Park, J Kim, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 63 (11), 1889-1897, 2016 | 37 | 2016 |
| An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier Y Park, J Song, Y Choi, C Lim, S Ahn, C Kim IEEE Journal of Solid-State Circuits 55 (9), 2468-2477, 2020 | 15 | 2020 |
| A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance J Maeng, M Shim, J Jeong, I Park, Y Park, C Kim IEEE Journal of Solid-State Circuits 55 (6), 1624-1636, 2019 | 9 | 2019 |
| A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs C Lim, Y Choi, Y Park, J Song, SS Ahn, S Park, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 68 (8), 3242-3253, 2021 | 6 | 2021 |
| A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique J Song, Y Park, C Lim, Y Choi, S Ahn, S Park, C Kim IEEE Journal of Solid-State Circuits 57 (5), 1492-1503, 2021 | 5 | 2021 |
| Time-interleaved analog-digital converter and calibration method for the same CW Kim, YS Park US Patent 9,780,802, 2017 | 4 | 2017 |
| 전력 효율적인 다중입력-단일인덕터-다중출력 에너지 하베스팅 전압 변환기를 위한 벅 및 벅-부스트 변환 모드 비교 김현진， 맹준영， 박인호， 임동주， 박윤수， 임채강， 안순성， 김철우 대한전자공학회 학술대회, 513-515, 2020 | | 2020 |
David Soonsung AhnLG Display, Korea University, Samsung DisplayVerified email at lgdisplay.com
