| Investigation of DPA resistance of block RAMs in cryptographic implementations on FPGAs S Shah, R Velegalati, JP Kaps, D Hwang 2010 International Conference on Reconfigurable Computing and FPGAs, 274-279, 2010 | 45 | 2010 |
| DPA resistant AES on FPGA using partial DDL JP Kaps, R Velegalati 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010 | 39 | 2010 |
| DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs R Velegalati, JP Kaps 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 21 | 2009 |
| Towards a flexible, opensource board for side-channel analysis (fobos) R Velegalati, JP Kaps Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI, 2013 | 20 | 2013 |
| Improving security of SDDL designs through interleaved placement on Xilinx FPGAs R Velegalati, JP Kaps 2011 21st International Conference on Field Programmable Logic and …, 2011 | 20 | 2011 |
| Introducing fobos: Flexible open-source board for side-channel analysis R Velegalati, JP Kaps Constructive Side-Channel Analysis and Secure Design (COSADE), Third …, 2012 | 19 | 2012 |
| Differential power analysis attack on FPGA implementation of AES R Velegalati, PS Yalla ECE 746 Statistical Signal Processing, 2008 | 18 | 2008 |
| Glitch detection in hardware implementations on fpgas using delay based sampling techniques R Velegalati, K Shah, JP Kaps 2013 Euromicro Conference on Digital System Design, 947-954, 2013 | 14 | 2013 |
| Electro magnetic fault injection in practice R Velegalati, R Van Spyk, J van Woudenberg International Cryptographic module conference (ICMC), 2013 | 14 | 2013 |
| Techniques to enable the use of block RAMs on FPGAs with dynamic and differential logic R Velegalati, JP Kaps 2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010 | 9 | 2010 |
| Flexible, Opensource workBench fOr Side-channel analysis (FOBOS) A Abdulgadir, W Diehl, R Velegalati, JP Kaps Proc. IEEE Int. Symp. Harwdare Oriented Secur. Trust (HOST), 2018 | 6 | 2018 |
| Securing light weight cryptographic implementations on FPGAs using dual rail with pre-charge logic R Velegalati | 5 | 2009 |
| Special Session: CAD for Hardware Security-Promising Directions for Automation of Security Assurance S Aftabjahani, M Tehranipoor, F Farahmandi, B Ahmed, R Kastner, ... 2023 IEEE 41st VLSI Test Symposium (VTS), 1-10, 2023 | 2 | 2023 |
| Differential fault analysis using symbolic execution J van Woudenberg, CB Breunesse, R Velegalati, P Yalla, S Gonzalez Proceedings of the 7th Software Security, Protection, and Reverse …, 2017 | 2 | 2017 |
| Developing an Integrated Environment for Detecting and Mitigating Side-channel and Fault Attacks on Hardware Platforms R Velegalati | 2 | 2015 |
| Improving CPU Fault Injection Simulations: Insights from RTL to Instruction-Level Models J van Woudenberg, R Velegalati, CB Breunesse, DV Riscure 2024 Workshop on Fault Detection and Tolerance in Cryptography (FDTC), 1-9, 2024 | 1 | 2024 |
| Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules B Brewster, E Homsirikamol, R Velegalati, K Gaj 2012 International Conference on Field-Programmable Technology, 113-118, 2012 | | 2012 |
| FDTC 2024 J Van Woudenberg, R Velegalati | | |
Panasayya YallaSecurity Analyst, Riscure North AmericaVerified email at riscure.com
