Rajesh Velegalati
Rajesh Velegalati
Security Analyst
Geverifieerd e-mailadres voor gmu.edu - Homepage
Geciteerd door
Geciteerd door
Investigation of DPA resistance of block RAMs in cryptographic implementations on FPGAs
S Shah, R Velegalati, JP Kaps, D Hwang
2010 International Conference on Reconfigurable Computing and FPGAs, 274-279, 2010
DPA resistant AES on FPGA using partial DDL
JP Kaps, R Velegalati
2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010
Improving security of SDDL designs through interleaved placement on Xilinx FPGAs
R Velegalati, JP Kaps
2011 21st International Conference on Field Programmable Logic and …, 2011
DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs
R Velegalati, JP Kaps
2009 International Conference on Field Programmable Logic and Applications …, 2009
Towards a flexible, opensource board for side-channel analysis (fobos)
R Velegalati, JP Kaps
Cryptographic architectures embedded in reconfigurable devices, CRYPTARCHI, 2013
Differential power analysis attack on FPGA implementation of AES
R Velegalati, PS Yalla
ECE 746 Statistical Signal Processing, 2008
Introducing fobos: Flexible open-source board for side-channel analysis
R Velegalati, JP Kaps
Constructive Side-Channel Analysis and Secure Design (COSADE), Third …, 2012
Electro magnetic fault injection in practice
R Velegalati, R Van Spyk, J van Woudenberg
International Cryptographic module conference (ICMC), 2013
Glitch detection in hardware implementations on FPGAs using delay based sampling techniques
R Velegalati, K Shah, JP Kaps
2013 Euromicro Conference on Digital System Design, 947-954, 2013
Techniques to enable the use of block RAMs on FPGAs with dynamic and differential logic
R Velegalati, JP Kaps
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
Flexible, Opensource workBench fOr Side-channel analysis (FOBOS)
A Abdulgadir, W Diehl, R Velegalati, JP Kaps
Proc. IEEE Int. Symp. Harwdare Oriented Secur. Trust (HOST), 2018
Securing light weight cryptographic implementations on FPGAs using dual rail with pre-charge logic
R Velegalati
Differential Fault Analysis Using Symbolic Execution
J van Woudenberg, CB Breunesse, R Velegalati, P Yalla, S Gonzalez
Proceedings of the 7th Software Security, Protection, and Reverse …, 2017
Developing an Integrated Environment for Detecting and Mitigating Side-channel and Fault Attacks on Hardware Platforms
R Velegalati
Special Session: CAD for Hardware Security-Promising Directions for Automation of Security Assurance
S Aftabjahani, M Tehranipoor, F Farahmandi, B Ahmed, R Kastner, ...
2023 IEEE 41st VLSI Test Symposium (VTS), 1-10, 2023
Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules
B Brewster, E Homsirikamol, R Velegalati, K Gaj
2012 International Conference on Field-Programmable Technology, 113-118, 2012
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