| A Maude framework for cache coherent multicore architectures S Bijo, EB Johnsen, KI Pun, SL Tapia Tarifa Rewriting Logic and Its Applications: 11th International Workshop, WRLA 2016 …, 2016 | 15 | 2016 |
| An operational semantics of cache coherent multicore architectures S Bijo, EB Johnsen, KI Pun, SLT Tarifa Proceedings of the 31st Annual ACM Symposium on Applied Computing, 1219-1224, 2016 | 12 | 2016 |
| A formal model of parallel execution on multicore architectures with multilevel caches S Bijo, EB Johnsen, KI Pun, SL Tapia Tarifa Formal Aspects of Component Software: 14th International Conference, FACS …, 2017 | 8 | 2017 |
| A formal model of data access for multicore architectures with multilevel caches S Bijo, EB Johnsen, KI Pun, SLT Tarifa Science of Computer Programming 179, 24-53, 2019 | 6 | 2019 |
| Deployment by construction for multicore architectures S Bijo, EB Johnsen, KI Pun, C Seidl, SLT Tarifa Leveraging Applications of Formal Methods, Verification and Validation …, 2018 | 2 | 2018 |
| Technical Report: Modelling Data Access Patterns with Atomic Sections for Multicore Architectures S Bijo, KI Pun, SLT Tarifa | | 2017 |
| An Operational Framework for Multilevel Cache Coherent Multicore Architectures⇤ S Bijo, EB Johnsen, KI Pun, SLT Tarifa Workshop on Programming Theory (NWPT’16), 9, 0 | | |
