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Michel Berkelaar
Michel Berkelaar
Delft University of Technology
Verified email at berkelaar.org
Title
Cited by
Cited by
Year
lp solve: a Mixed Integer Linear Program solver
M Berkelaar, J Dirks
895*1997
Transistor sizing in MOS digital circuits with linear programming
M Berkelaar, JAG Jess
Proc. of the European Design Automation Conference,(Mierlo, The Netherlands …, 1990
2231990
LP solve: Opern Source (Mixed-Integer) Linear Programming System (2007)
M Berkelaar
http://lpsolve. sourceforge. net/5.5/, 2004
179*2004
Statistical delay calculation, a linear time method
M Berkelaar
proc. TAU 97, 15-24, 1997
1411997
Gate sizing using a statistical delay model
E Jacobs, MRCM Berkelaar
Proceedings of the conference on Design, automation and test in Europe, 283-291, 2000
1392000
lpSolve: Interface to ‘Lp_solve’v. 5.5 to solve linear/integer programs
M Berkelaar, K Eikland, P Notebaert
R package version 5, 13, 2015
1262015
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator
MRCM Berkelaar, PHW Buurman, JAG Jess
IEEE transactions on computer-aided design of integrated circuits and …, 1996
761996
Technology mapping for standard-cell generators.
MRCM Berkelaar, JAG Jess
ICCAD, 470-473, 1988
681988
lpSolve: interface to ‘Lp_solve’v. 5.5 to solve linear/integer programs. R package version 5.6. 13
M Berkelaar, J Dirks, K Eikland, P Notebaert, J Ebert, H Gourvest
Vienna, Austria: R Foundation for Statistical Computing, 2015
362015
Stochastic analysis of deep-submicrometer CMOS process for reliable circuits designs
A Zjajo, Q Tang, M Berkelaar, JP de Gyvez, A Di Bucchianico, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (1), 164-175, 2010
292010
Efficient use of large don't cares in high-level and logic synthesis
RA Bergamaschi, D Brand, L Stok, M Berkelaar, S Prakash
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
291995
Using gate sizing to reduce glitch power
E Jacobs, M Berkelaar
Proceedings of the Prorisc/IEEE Workshop on Circuits, Systems and Signal …, 1996
281996
RDE-based transistor-level gate simulation for statistical static timing analysis
Q Tang, A Zjajo, M Berkelaar, N van der Meijs
Proceedings of the 47th Design Automation Conference, 787-792, 2010
212010
Efficient orthonormality testing for synthesis with pass-transistor selectors
M Berkelaar, LPPP Van Ginneken
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
181995
Area-power-delay trade-off in logic synthesis.
MRCM Berkelaar
181994
others. lpSolve: Interface to ‘Lp_solve’v. 5.5 to Solve Linear/Integer Programs; 2015
M Berkelaar
URL http://CRAN. R-project. org/package= lpSolve. R package version 5 (11), 5.2, 0
16
Efficient and effective redundancy removal for million-gate circuits
M Berkelaar, K van Eijk
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
152002
Improved state assignment for burst mode finite state machines
J Rutten, MRCM Berkelaar
Proceedings Third International Symposium on Advanced Research in …, 1997
151997
others (2015)“lpSolve: Interface to Lpsolve v. 5.5 to solve linear–integer programs”. R package version 5.6. 13
M Berkelaar
15
Logic Optimization with Technology and Delay in Mind
JFM Theeuwen, M Berkelaar
Proceedings of the International Workshop on Logic Synthesis, 1987
141987
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