Michel Berkelaar
Michel Berkelaar
Delft University of Technology
Verified email at berkelaar.org
Title
Cited by
Cited by
Year
lp solve: a Mixed Integer Linear Program solver
M Berkelaar, J Dirks
781*1997
Gate sizing in MOS digital circuits with linear programming
MRCM Berkelaar, JAG Jess
Proceedings of the conference on European design automation, 217-221, 1990
2021990
Statistical delay calculation, a linear time method
M Berkelaar
Proceedings of TAU 97, 15-24, 1997
1351997
Gate sizing using a statistical delay model
E Jacobs, MRCM Berkelaar
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000
1242000
LP solve: Opern Source (Mixed-Integer) Linear Programming System (2007)
M Berkelaar
http://lpsolve. sourceforge. net/5.5/, 2004
123*2004
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator
MRCM Berkelaar, PHW Buurman, JAG Jess
IEEE transactions on computer-aided design of integrated circuits and …, 1996
651996
Technology mapping for standard-cell generators.
MRCM Berkelaar, JAG Jess
ICCAD, 470-473, 1988
621988
Using gate sizing to reduce glitch power
E Jacobs, M Berkelaar
Proceedings of the Prorisc/IEEE Workshop on Circuits, Systems and Signal …, 1996
301996
Efficient use of large don't cares in high-level and logic synthesis
RA Bergamaschi, D Brand, L Stok, M Berkelaar, S Prakash
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
261995
Stochastic analysis of deep-submicrometer CMOS process for reliable circuits designs
A Zjajo, Q Tang, M Berkelaar, JP De Gyvez, A Di Bucchianico, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (1), 164-175, 2010
242010
RDE-based transistor-level gate simulation for statistical static timing analysis
Q Tang, A Zjajo, M Berkelaar, N van der Meijs
Proceedings of the 47th Design Automation Conference, 787-792, 2010
212010
Area-power-delay trade-off in logic synthesis.
MRCM Berkelaar
191994
Efficient orthonormality testing for synthesis with pass-transistor selectors
M Berkelaar, LPPP Van Ginneken
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
181995
lpSolve: interface to ‘Lp_solve’v. 5.5 to solve linear/integer programs. R package version 5.6. 13
M Berkelaar, J Dirks, K Eikland, P Notebaert, J Ebert, H Gourvest
162015
lpsolve2. 2
M Berkelaar, J Dirks
Eindhoven University of Technology, Design Automation Section, 0
15
Efficient and effective redundancy removal for million-gate circuits
M Berkelaar, K van Eijk
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
142002
Improved state assignment for burst mode finite state machines
J Rutten, MRCM Berkelaar
Proceedings Third International Symposium on Advanced Research in …, 1997
141997
Transistor level waveform evaluation for timing analysis
Q Tang, A Zjajo, M Berkelaar, NP Van Der Meijs
VARI, The European workshops on CMOS Variability, 2010
122010
others (2015)“lpSolve: Interface to Lpsolve v. 5.5 to solve linear–integer programs”. R package version 5.6. 13
M Berkelaar
12
others. lpSolve: Interface to ‘Lp_solve’v. 5.5 to Solve Linear/Integer Programs; 2015
M Berkelaar
R package version 5 (5), 0
12
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