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Marcin Rogawski
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Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs
K Gaj, E Homsirikamol, M Rogawski
International Workshop on Cryptographic Hardware and Embedded Systems, 264-278, 2010
1502010
ATHENa-automated tool for hardware evaluation: Toward fair and comprehensive benchmarking of cryptographic hardware using FPGAs
K Gaj, JP Kaps, V Amirineni, M Rogawski, E Homsirikamol, BY Brewster
2010 International Conference on Field Programmable Logic and Applications …, 2010
1052010
Comprehensive evaluation of high-speed and medium-speed implementations of five SHA-3 finalists using Xilinx and Altera FPGAs
K Gaj, E Homsirikamol, M Rogawski, R Shahid, MU Sharif
Cryptology ePrint Archive, 2012
902012
Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs
E Homsirikamol, M Rogawski, K Gaj
International Workshop on Cryptographic Hardware and Embedded Systems, 491-506, 2011
552011
Comparing hardware performance of round 3 SHA-3 candidates using multiple hardware architectures in Xilinx and Altera FPGAs
E Homsirikamol, M Rogawski, K Gaj
Ecrypt II Hash Workshop 2011, 1-15, 2011
442011
Security margin evaluation of SHA-3 contest finalists through SAT-based attacks
E Homsirikamol, P Morawiecki, M Rogawski, M Srebrny
IFIP International Conference on Computer Information Systems and Industrial …, 2012
352012
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates
R Shahid, MU Sharif, M Rogawski, K Gaj
2011 International Conference on Field-Programmable Technology, 1-9, 2011
322011
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates
R Shahid, MU Sharif, M Rogawski, K Gaj
2011 International Conference on Field-Programmable Technology, 1-9, 2011
322011
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates
R Shahid, MU Sharif, M Rogawski, K Gaj
2011 International Conference on Field-Programmable Technology, 1-9, 2011
322011
Comprehensive comparison of hardware performance of fourteen round 2 SHA-3 candidates with 512-bit outputs using field programmable gate arrays
K Gaj, E Homsirikamol, M Rogawski
2nd SHA-3 Candidate Conference, Santa Barbara, August, 23-24, 2010
322010
Lessons learned from designing a 65nm ASIC for evaluating third round SHA-3 candidates
FK Gürkaynak, K Gaj, B Muheim, E Homsirikamol, C Keller, M Rogawski, ...
Third SHA-3 Candidate Conference, 1-22, 2012
292012
Hardware evaluation of estream candidates: grain, lex, mickey128, salsa20 and trivium
M Rogawski
State of the Art of Stream Ciphers Workshop (SASC 2007), eSTREAM, ECRYPT …, 2007
272007
Efficient hardware accelerator for IPSec based on partial reconfiguration on Xilinx FPGAs
A Salman, M Rogawski, JP Kaps
2011 International Conference on Reconfigurable Computing and FPGAs, 242-248, 2011
262011
ICEPOLE: high-speed, hardware-oriented authenticated encryption
P Morawiecki, K Gaj, E Homsirikamol, K Matusiewicz, J Pieprzyk, ...
International Workshop on Cryptographic Hardware and Embedded Systems, 392-413, 2014
202014
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off
MU Sharif, R Shahid, K Gaj, M Rogawski
2016 26th International Conference on Field Programmable Logic and …, 2016
132016
Area-time efficient implementation of the elliptic curve method of factoring in reconfigurable hardware for application in the number field sieve
K Gaj, S Kwon, P Baier, P Kohlbrenner, H Le, M Khaleeluddin, ...
IEEE Transactions on Computers 59 (9), 1264-1280, 2010
132010
Area-time efficient implementation of the elliptic curve method of factoring in reconfigurable hardware for application in the number field sieve
K Gaj, S Kwon, P Baier, P Kohlbrenner, H Le, M Khaleeluddin, ...
IEEE Transactions on Computers 59 (9), 1264-1280, 2010
132010
ICEPOLE v1
P Morawiecki, K Gaj, E Homsirikamol, K Matusiewicz, J Pieprzyk, ...
submitted to the CAESAR competition, 2015
112015
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs
M Rogawski, E Homsirikamol, K Gaj
2014 24th International Conference on Field Programmable Logic and …, 2014
112014
A high-speed unified hardware architecture for AES and the SHA-3 candidate Grøstl
M Rogawski, K Gaj
2012 15th Euromicro Conference on Digital System Design, 568-575, 2012
112012
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